公开(公告)号：EP3118892A4

公开(公告)日：2017-04-12

申请号：EP14885109

申请日：2014-12-26

申请人： THRUCHIP JAPAN INC

发明人： KURODA TADAHIRO

IPC分类号： H01L21/768 ,  H01L21/48 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC分类号： H01L25/0652 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/092 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/80006 ,  H01L2224/80203 ,  H01L2224/8083 ,  H01L2224/80986 ,  H01L2224/81005 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/9222 ,  H01L2224/92225 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/19107 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/20752

摘要： The invention relates to a multilayer semiconductor integrated circuit device which is provided with a smaller space for a three-dimensional multilayer configuration at a lower cost and with a sufficient power supply quality. A first semiconductor integrated circuit device is provided with a first penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the first power supply potential, and a second penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the second power supply potential. A second semiconductor integrated circuit device having a first electrode and a second electrode is layered on top of the first semiconductor integrated circuit device so that the first electrode and the second electrode are respectively connected to the first penetrating semiconductor region and the second penetrating semiconductor region.

摘要翻译： 本发明涉及一种多层半导体集成电路器件，其以较低的成本和足够的电源质量为三维多层结构提供较小的空间。 第一半导体集成电路器件设置有在厚度方向上穿过第一半导体本体并连接到第一电源电位的第一穿透半导体区域，以及穿过第一半导体本体的第二穿透半导体区域 厚度方向并连接到第二电源电位。 具有第一电极和第二电极的第二半导体集成电路器件层叠在第一半导体集成电路器件的顶部上，使得第一电极和第二电极分别连接到第一穿透半导体区域和第二穿透半导体区域。