公开(公告)号：EP3096350A1

公开(公告)日：2016-11-23

申请号：EP16166762.1

申请日：2016-04-24

申请人： MediaTek Inc.

发明人： LIN, Tzu-Hung ,  HSIAO, Ching-Wen ,  PENG, I-Hsuan

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L25/10 ,  H01L23/538 ,  H01L23/31

CPC分类号： H01L25/16 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76879 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/80 ,  H01L24/89 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02317 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/73259 ,  H01L2224/80003 ,  H01L2224/80006 ,  H01L2224/802 ,  H01L2224/8083 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/37001 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/80001

摘要： A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die and includes a first conductive trace. The semiconductor package assembly also includes a second semiconductor package bonded to the first semiconductor package. The second semiconductor package includes a second semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. A second RDL structure is coupled to the second semiconductor die and includes a second conductive trace. The first conductive trace is in direct contact with the second conductive trace.

摘要翻译： 提供半导体封装组件。 该半导体封装组件包括第一半导体封装。 第一半导体封装包括第一半导体管芯。 第一重新分布层（RDL）结构耦合到第一半导体管芯且包括第一导电迹线。 半导体封装组件还包括结合到第一半导体封装的第二半导体封装。 第二半导体封装包括第二半导体管芯。 第二半导体管芯的有源表面面向第一半导体管芯的有源表面。 第二RDL结构耦合到第二半导体管芯且包括第二导电迹线。 第一导电迹线与第二导电迹线直接接触。

公开(公告)号：EP0330896A3

公开(公告)日：1991-01-09

申请号：EP89102448.1

申请日：1989-02-13

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： Schwarzbauer, Herbert, Dr.rer.nat.

IPC分类号： H01L21/603

CPC分类号： H01L24/75 ,  H01L24/80 ,  H01L24/83 ,  H01L2224/75315 ,  H01L2224/8083 ,  H01L2224/81005 ,  H01L2224/8319 ,  H01L2224/83801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1301 ,  H01L2924/351 ,  H01L2924/00

摘要： Zum Befestigen von Halbleiterbauelementen (3), insbesondere Leistungshalbleitern, auf Substraten (1) wird ein Diffusions­schweißverfahren angegeben, bei dem die zu verbindenden Flä­chen, die mit einer Edelmetall-Kontaktierungsschicht ver­sehen sind, bei gemäßigter Temperatur von etwa 150 bis 250°C mit mindestens 500 kp/cm² zusammengepreßt werden. Bauelemente (3) mit strukturierter Oberseite können mit Substraten verbun­den werden, wenn sie gemeinsam mit einem Körper (17, 18) aus elastisch verformbarem Material, z.B. Silikonkautschuk, in eine durch einen bewegbaren Stempel (21) abgeschlossene, den Anpress­druck übertragende Aufnahmekammer (15a, 15b, 21) eingelegt wer­den, wobei der deformierbare Körper (17, 18) beim Erreichen des Anpressdrucks den verbleibenden Innenraum der Aufnahmekammer vollständig ausfüllt.

公开(公告)号：EP1986233A3

公开(公告)日：2010-08-04

申请号：EP08006005.6

申请日：1998-04-03

申请人： Leedy, Glenn, J.

发明人： Leedy, Glenn, J.

IPC分类号： H01L25/065 ,  H01L21/768 ,  H01L27/06 ,  H01L27/108 ,  H01L21/822 ,  H01L27/105 ,  H01L21/603 ,  G11C29/00 ,  G11C29/44

CPC分类号： H01L27/10897 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C29/44 ,  G11C29/81 ,  G11C29/846 ,  G11C29/848 ,  H01L23/481 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/8083 ,  H01L2225/06541 ,  H01L2924/01079 ,  Y10S438/977 ,  H01L2924/00014

摘要： An on-chip reconfigurable memory is disclosed, comprising: a plurality of data lines, a plurality of gate lines, an array of memory cells, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines, a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment and a controller for determining that at least one of said memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.

公开(公告)号：EP0975472A1

公开(公告)日：2000-02-02

申请号：EP98914558.6

申请日：1998-04-03

申请人： Leedy, Glenn, J.

发明人： Leedy, Glenn, J.

IPC分类号： B44C1/22 ,  C09J5/02 ,  C23F1/02

CPC分类号： H01L27/10897 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C29/44 ,  G11C29/81 ,  G11C29/846 ,  G11C29/848 ,  H01L23/481 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/8083 ,  H01L2225/06541 ,  H01L2924/01079 ,  Y10S438/977 ,  H01L2924/00014

摘要： A Three Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers (103) such that each layer may be separately optimized. One control logic circuit (101) suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory (100) involves thinning of the memory circuit (103) to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

公开(公告)号：EP0330896A2

公开(公告)日：1989-09-06

申请号：EP89102448.1

申请日：1989-02-13

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： Schwarzbauer, Herbert, Dr.rer.nat.

IPC分类号： H01L21/603

CPC分类号： H01L24/75 ,  H01L24/80 ,  H01L24/83 ,  H01L2224/75315 ,  H01L2224/8083 ,  H01L2224/81005 ,  H01L2224/8319 ,  H01L2224/83801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1301 ,  H01L2924/351 ,  H01L2924/00

摘要： Zum Befestigen von Halbleiterbauelementen (3), insbesondere Leistungshalbleitern, auf Substraten (1) wird ein Diffusions­schweißverfahren angegeben, bei dem die zu verbindenden Flä­chen, die mit einer Edelmetall-Kontaktierungsschicht ver­sehen sind, bei gemäßigter Temperatur von etwa 150 bis 250°C mit mindestens 500 kp/cm² zusammengepreßt werden. Bauelemente (3) mit strukturierter Oberseite können mit Substraten verbun­den werden, wenn sie gemeinsam mit einem Körper (17, 18) aus elastisch verformbarem Material, z.B. Silikonkautschuk, in eine durch einen bewegbaren Stempel (21) abgeschlossene, den Anpress­druck übertragende Aufnahmekammer (15a, 15b, 21) eingelegt wer­den, wobei der deformierbare Körper (17, 18) beim Erreichen des Anpressdrucks den verbleibenden Innenraum der Aufnahmekammer vollständig ausfüllt.

摘要翻译： 提供了一种用于附连半导体部件（3），特别是功率半导体，所述衬底（1）扩散焊接工艺。 在此过程中，待连接的表面，提供了与贵金属接触层，在至少500千克力/厘米<2>被压到一起在约150中等温度至（3），其具有250℃的组件 这是由可动密封的结构上侧可接合到所述基板，如果它们被放置，用可弹性变形材料制成的主体（17，18）在一起，例如硅橡胶，在接收室（15A，15B，21）的所有 的（21）和发送所述的接触压力。 在达到接触压力，接收室的剩余内部空间被完全地调用由变形体（17，18）填充的。 ... ...

公开(公告)号：EP3118892A4

公开(公告)日：2017-04-12

申请号：EP14885109

申请日：2014-12-26

申请人： THRUCHIP JAPAN INC

发明人： KURODA TADAHIRO

IPC分类号： H01L21/768 ,  H01L21/48 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC分类号： H01L25/0652 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/092 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/80006 ,  H01L2224/80203 ,  H01L2224/8083 ,  H01L2224/80986 ,  H01L2224/81005 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/9222 ,  H01L2224/92225 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/19107 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/20752

摘要： The invention relates to a multilayer semiconductor integrated circuit device which is provided with a smaller space for a three-dimensional multilayer configuration at a lower cost and with a sufficient power supply quality. A first semiconductor integrated circuit device is provided with a first penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the first power supply potential, and a second penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the second power supply potential. A second semiconductor integrated circuit device having a first electrode and a second electrode is layered on top of the first semiconductor integrated circuit device so that the first electrode and the second electrode are respectively connected to the first penetrating semiconductor region and the second penetrating semiconductor region.

摘要翻译： 本发明涉及一种多层半导体集成电路器件，其以较低的成本和足够的电源质量为三维多层结构提供较小的空间。 第一半导体集成电路器件设置有在厚度方向上穿过第一半导体本体并连接到第一电源电位的第一穿透半导体区域，以及穿过第一半导体本体的第二穿透半导体区域 厚度方向并连接到第二电源电位。 具有第一电极和第二电极的第二半导体集成电路器件层叠在第一半导体集成电路器件的顶部上，使得第一电极和第二电极分别连接到第一穿透半导体区域和第二穿透半导体区域。

公开(公告)号：EP3111467A2

公开(公告)日：2017-01-04

申请号：EP15706806.5

申请日：2015-02-26

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： GONDCHARTON, Paul ,  BENAISSA, Lamine ,  IMBERT, Bruno ,  MORICEAU, Hubert

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/98 ,  H01L23/485

CPC分类号： H01L24/83 ,  H01L21/185 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0381 ,  H01L2224/03845 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/2745 ,  H01L2224/2755 ,  H01L2224/27845 ,  H01L2224/29147 ,  H01L2224/80055 ,  H01L2224/80357 ,  H01L2224/8083 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/8092 ,  H01L2224/80948 ,  H01L2224/83895 ,  H01L2225/06524 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01008 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01017 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2924/049 ,  H01L2924/00012

摘要： Process for producing a structure by direct adhesive bonding of two elements comprising the production of the elements to be assembled and the assembly of said elements, in which the production of the elements to be assembled comprises the steps: - deposition on a substrate of a TiN layer by physical vapour deposition, - deposition of a copper layer on the TiN layer, and in which the assembly of said elements comprises the steps: - polishing the surfaces of the copper layers intended to come into contact so that they have a roughness of less than 1 nm RMS and hydrophilic properties, - bringing said surfaces into contact, - storing said structure at atmospheric pressure and at ambient temperature.

摘要翻译： 待组装和元件的组装生产的元件的：一种用于通过两个元件，所述方法包括直接键合制造结构的方法。 生产的元件的组装，包括：在TiN层上的铜层的通过物理气相沉积TiN层，和沉积的底物沉积。 的元件的组件包括：抛光预期会接触，从而thatthey具有小于1个纳米RMS和亲水性能的粗糙度铜层的表面，使表面接触，并在大气压下和在存放结构 环境温度。

公开(公告)号：EP1986233A2

公开(公告)日：2008-10-29

申请号：EP08006005.6

申请日：1998-04-03

申请人： Leedy, Glenn, J.

发明人： Leedy, Glenn, J.

IPC分类号： H01L25/065 ,  H01L21/768 ,  H01L27/06 ,  H01L27/108 ,  H01L21/822 ,  H01L27/105 ,  H01L21/603 ,  G11C29/00

CPC分类号： H01L27/10897 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C29/44 ,  G11C29/81 ,  G11C29/846 ,  G11C29/848 ,  H01L23/481 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/8083 ,  H01L2225/06541 ,  H01L2924/01079 ,  Y10S438/977 ,  H01L2924/00014

摘要： An on-chip reconfigurable memory is disclosed, comprising: a plurality of data lines, a plurality of gate lines, an array of memory cells, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines, a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment and a controller for determining that at least one of said memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.

摘要翻译： 公开了一种片上可重构存储器，包括：多个数据线，多条栅极线，存储器单元阵列，每个存储单元存储数据值，并且包括用于将该数据值耦合到所述数据线之一的电路 响应于所述栅线之一的选择，用于使栅极线用于存储器操作的栅极线选择电路，所述栅极线选择电路包括可编程门以接收一个或多个所述栅极线的地址分配，所述地址 用于确定为每个编程的地址分配选择哪个所述栅极线的分配以及用于确定至少一个所述存储单元是有缺陷的控制器，并且用于在至少一个实例中改变所述栅极线的所述地址分配以消除参考 该栅极线导致该缺陷存储单元将数据值耦合到所述数据线之一。

公开(公告)号：EP3118892B1

公开(公告)日：2018-05-02

申请号：EP14885109.0

申请日：2014-12-26

申请人： Thruchip Japan Inc.

发明人： KURODA, Tadahiro

IPC分类号： H01L21/48 ,  H01L21/768 ,  H01L23/48 ,  H01L23/538 ,  H01L23/64 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/06 ,  H01L27/092

CPC分类号： H01L25/0652 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/18 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/092 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/80006 ,  H01L2224/80203 ,  H01L2224/8083 ,  H01L2224/80986 ,  H01L2224/81005 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/9222 ,  H01L2224/92225 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/19107 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/20752

摘要： The invention relates to a multilayer semiconductor integrated circuit device which is provided with a smaller space for a three-dimensional multilayer configuration at a lower cost and with a sufficient power supply quality. A first semiconductor integrated circuit device is provided with a first penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the first power supply potential, and a second penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the second power supply potential. A second semiconductor integrated circuit device having a first electrode and a second electrode is layered on top of the first semiconductor integrated circuit device so that the first electrode and the second electrode are respectively connected to the first penetrating semiconductor region and the second penetrating semiconductor region.

公开(公告)号：EP3118892A1

公开(公告)日：2017-01-18

申请号：EP14885109.0

申请日：2014-12-26

申请人： Thruchip Japan Inc.

发明人： KURODA, Tadahiro

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC分类号： H01L25/0652 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/18 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/092 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/80006 ,  H01L2224/80203 ,  H01L2224/8083 ,  H01L2224/80986 ,  H01L2224/81005 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/9222 ,  H01L2224/92225 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/19107 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/20752

摘要： The invention relates to a multilayer semiconductor integrated circuit device which is provided with a smaller space for a three-dimensional multilayer configuration at a lower cost and with a sufficient power supply quality. A first semiconductor integrated circuit device is provided with a first penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the first power supply potential, and a second penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the second power supply potential. A second semiconductor integrated circuit device having a first electrode and a second electrode is layered on top of the first semiconductor integrated circuit device so that the first electrode and the second electrode are respectively connected to the first penetrating semiconductor region and the second penetrating semiconductor region.

摘要翻译： 本发明涉及一种多层半导体集成电路器件，其以较低的成本和足够的电源质量为三维多层结构提供较小的空间。 第一半导体集成电路器件设置有第一贯穿半导体区域和第二贯穿半导体区域，第一贯穿半导体区域在厚度方向上贯穿第一半导体本体并且连接到第一电源电位，第二贯穿半导体区域贯穿第一半导体本体 厚度方向并且连接到第二电源电位。 具有第一电极和第二电极的第二半导体集成电路器件层叠在第一半导体集成电路器件的顶部上，使得第一电极和第二电极分别连接到第一穿透半导体区域和第二穿透半导体区域。