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公开(公告)号：EP3223303A1
公开(公告)日：2017-09-27
申请号：EP15861337.2
申请日：2015-11-17
发明人： TORIMI, Satoshi , SHINOHARA, Masato , TERAMOTO, Youji , YABUKI, Norihito , NOGAMI, Satoru , KANEKO, Tadaaki , ASHIDA, Koji , KUTSUMA, Yasunori
IPC分类号： H01L21/302 , C30B29/36 , C30B33/12
CPC分类号： H01L21/30604 , C30B29/36 , C30B33/12 , C30B35/002 , H01L21/302 , H01L21/67063
摘要： Provided is a method for controlling the rate of etching of a SiC substrate based on a composition of a storing container. The etching method of the present invention is for etching the SiC substrate by heating the SiC substrate under Si vapor pressure, in a state where the SiC substrate is stored in a crucible. The crucible is formed of a tantalum metal, and has a tantalum carbide layer provided on an internal space side of the tantalum metal, and a tantalum silicide layer provided on the side further toward the internal space side than the tantalum carbide layer. The rate of etching of the SiC substrate is controlled based on difference in a composition of the tantalum silicide layer.
摘要翻译： 提供了一种基于储存容器的组成来控制SiC衬底的蚀刻速率的方法。 本发明的蚀刻方法用于在将SiC基板收纳在坩埚中的状态下，通过在Si蒸气压下加热SiC基板来对SiC基板进行蚀刻。 坩埚由钽金属形成，并且具有设置在钽金属的内部空间侧上的碳化钽层和设置在比碳化钽层更靠近内部空间侧的侧面上的硅化钽层。 基于钽硅化物层的组成差异来控制SiC衬底的蚀刻速率。
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公开(公告)号：EP3222759A1
公开(公告)日：2017-09-27
申请号：EP15861692.0
申请日：2015-11-17
发明人： KANEKO, Tadaaki , ASHIDA, Koji , KUTSUMA, Yasunori , TORIMI, Satoshi , SHINOHARA, Masato , TERAMOTO, Youji , YABUKI, Norihito , NOGAMI, Satoru
IPC分类号： C30B33/12 , C30B29/36 , H01L21/302
CPC分类号： H01L21/30621 , C30B29/36 , C30B33/12 , H01L21/0445 , H01L21/302 , H01L21/304
摘要： Provided is a surface treatment method for a SiC substrate (40), the method being capable of controlling whether to generate a step bunching or the type of step bunching that is generated. In the surface treatment method in which the surface of the SiC substrate (40) is etched by heating the SiC substrate (40) under Si vapor pressure, an etching mode and an etching depth which are determined at least on the basis of an etching rate, are controlled to etch the SiC substrate (40), so that a surface pattern of the SiC substrate (40) after etching treatment is controlled.
摘要翻译： 提供了一种用于SiC衬底（40）的表面处理方法，该方法能够控制是产生台阶聚集还是产生的台阶聚集的类型。 在通过在Si蒸气压下加热SiC衬底（40）来对SiC衬底（40）的表面进行蚀刻的表面处理方法，蚀刻模式和蚀刻深度至少基于蚀刻速率 被控制以蚀刻SiC衬底（40），从而控制蚀刻处理后的SiC衬底（40）的表面图案。
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公开(公告)号：EP4403677A3
公开(公告)日：2024-08-21
申请号：EP24162314.9
申请日：2020-08-05
发明人： KANEKO, Tadaaki , KOJIMA, Kiyoshi
IPC分类号： C30B29/36 , C30B23/06 , C30B33/12 , H01L21/203 , C30B23/02 , C30B25/18 , C30B33/02 , H01L21/02
CPC分类号： C30B29/36 , H01L21/02529 , H01L21/02658 , H01L21/02378 , H01L21/02631 , H01L21/02019 , C30B33/02 , C30B33/12 , C30B23/025 , C30B23/063 , C30B25/186
摘要： An object of the present invention is to provide a novel technology capable of achieving high-quality SiC seed crystal, SiC ingot, SiC wafer and SiC wafer with an epitaxial film. The present invention, which solves the above object, is a method for producing a SiC seed crystal for growth of a SiC ingot, the method including a heat treatment step of heat-treating a SiC single crystal in an atmosphere containing Si element and C element. As described above, by heat-treating the SiC single crystal in an atmosphere containing the Si element and the C element, it is possible to produce a high-quality SiC seed crystal in which strain and crystal defects are suppressed.
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公开(公告)号：EP4276884A1
公开(公告)日：2023-11-15
申请号：EP22904341.9
申请日：2022-12-09
IPC分类号： H01L21/304 , H01L21/66
摘要： An object of the present invention is to provide a novel technology capable of evaluating a subsurface damaged layer without destroying a semiconductor substrate. As means for solving this object, the present invention includes a measurement step of causing laser light having penetration characteristics to be incident from a surface of a semiconductor substrate having a subsurface damaged layer under the surface and measuring an intensity of scattered light scattered under the surface, and an evaluation step of evaluating the subsurface damaged layer on the basis of the intensity of the scattered light obtained in the measurement step.
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公开(公告)号：EP4239111A1
公开(公告)日：2023-09-06
申请号：EP21886282.9
申请日：2021-10-27
发明人： KANEKO, Tadaaki , DOJIMA, Daichi
摘要： An object of the present invention is to provide a novel evaluation method suitable for evaluating a SiC substrate having a large diameter.
The present invention is a method for evaluating a silicon carbide substrate, the method comprising an image acquisition step of acquiring an image by making an electron beam incident at an incident angle inclined with respect to a normal line of a {0001} plane of a silicon carbide substrate, wherein the incident angle is 10° or less.-
公开(公告)号：EP4137621A1
公开(公告)日：2023-02-22
申请号：EP21788223.2
申请日：2021-03-30
发明人： KANEKO, Tadaaki , DOJIMA, Daichi
摘要： The problem to be solved by the present invention is to provide novel technology capable of suppressing the introduction of displacement to a growth layer. The present invention, which solves the abovementioned problem, pertains to a method for manufacturing a semiconductor substrate, the mehod including: a processing step for removing a portion of a base substrate and forming a pattern that includes a minor angle; and a crystal growth step for forming a growth layer on the base substrate where the patter has been formed. In addition, the present invention pertains to a method for suppressing the introduction of displacement to a growth layer, the method including a processing step for removing a portion of the base substrate and forming a pattern that includes a minor angle prior to forming the growth layer on the base substrate.
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7.发明公开
公开(公告)号：EP3960912A1
公开(公告)日：2022-03-02
申请号：EP20793980.2
申请日：2020-04-24
发明人： KANEKO, Tadaaki
摘要： The present invention addresses the problem of providing a novel method for manufacturing a SiC substrate, and a manufacturing device for said method. The present invention realizes: a method for manufacturing a SiC substrate, comprising heating two mutually opposing SiC single-crystal substrates and transporting a raw material from one SiC single-crystal substrate to the other SiC single-crystal substrate; and a manufacturing device for said method. Through the present invention, each of the mutually opposing SiC single-crystal substrate surfaces can be used as a raw material for crystal growth of the other SiC single-crystal substrate surface, and it is therefore possible to realize a highly economical method for manufacturing a SiC substrate.
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公开(公告)号：EP3375914B1
公开(公告)日：2020-06-24
申请号：EP16863829.4
申请日：2016-11-08
发明人： KANEKO, Tadaaki , KUTSUMA, Yasunori , ASHIDA, Koji
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9.发明公开
公开(公告)号：EP4415025A1
公开(公告)日：2024-08-14
申请号：EP22878362.7
申请日：2022-09-26
发明人： KANEKO, Tadaaki , KOJIMA, Kiyoshi
IPC分类号： H01L21/205 , C30B29/36
CPC分类号： C30B29/36 , H01L21/2015
摘要： An object of the present invention is to provide a novel technique for improving an activation rate of dopant of an epitaxial layer. Another object of the present invention is to provide a novel technique for suppressing variation in activation rate of dopant in the epitaxial layer.
The present invention is a method for improving the activation rate of dopant of an epitaxial layer 20, including a growth step S10 of growing the epitaxial layer 20 having the dopant on a bulk layer 10 under an equilibrium vapor pressure environment.-
公开(公告)号：EP4279642A1
公开(公告)日：2023-11-22
申请号：EP22739360.0
申请日：2022-01-07
发明人： KANEKO, Tadaaki , KOJIMA, Kiyoshi
摘要： The present invention addresses the problem of providing a novel technology for measuring an etching amount in heat treatment in which growth and etching proceed simultaneously. The present invention includes: a first substrate thickness measuring step S10 for measuring the thickness 10D of a to-be-heat-treated semiconductor substrate 10; a second substrate thickness measuring step S20 for measuring the thickness 20D of a heat-treated semiconductor substrate 20; a growth layer thickness measuring step S30 for measuring the thickness 21D of a growth layer 21 which has gone through crystal growth by heat treatment; and an etching amount calculating step S40 for calculating the etching amount ED on the basis of the thickness 10D of the to-be-heat-treated semiconductor substrate 10, the thickness 20D of the heat-treated semiconductor substrate 20, and the thickness 21D of the growth layer 21.
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