公开(公告)号：EP1079394A4

公开(公告)日：2001-07-11

申请号：EP99913705

申请日：1999-04-19

申请人： ULTRACLEAN TECHNOLOGY RES INST ,  OHMI TADAHIRO ,  SHIBATA TADASHI

发明人： OHMI TADAHIRO ,  SHIBATA TADASHI ,  WEE KENG HOONG ,  YONEZAWA TAKEMI ,  NOZAWA TOSHIYUKI ,  NITTA TAKAHISA

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C27/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C11/5628 ,  G11C27/005 ,  G11C2211/5613

摘要： A semiconductor circuit of large-scale integration for storing analog data and multivalued data accurately at high speed. The semiconductor circuit comprises memory cells for analog and multivalued signals, a read circuit provided with an output to produce voltage indicating a value stored in the memory cell, a comparator provided with an output to produce an end-of-write signal when the voltage at the output of the read circuit becomes equal to a predetermined voltage, a write voltage control circuit having an input for receiving analog and multivalued voltage as write voltage of the memory cell and having an output for producing voltage corresponding to the voltage value, and a write voltage switch circuit for supplying the output voltage from the write voltage control circuit to the memory cell until the end-of-write signal appears at the output of the comparator.

公开(公告)号：EP1039372A4

公开(公告)日：2005-02-02

申请号：EP98961396

申请日：1998-12-17

申请人： ULTRACLEAN TECHNOLOGY RES INST ,  OHMI TADAHIRO ,  I & F INC

发明人： OHMI TADAHIRO ,  IMAI MAKOTO ,  NOZAWA TOSHIYUKI ,  FUJIBAYASHI MASANORI ,  KOTANI KOJI ,  SHIBATA TADASHI ,  NITTA TAKAHISA

IPC分类号： G06F7/00 ,  G06F7/48 ,  G06F7/50 ,  G06F7/506

CPC分类号： G06F7/4824 ,  G06F7/506

摘要： A semiconductor circuit for arithmetic operation, which uses a reduced circuit area and provides high-speed processing by restricting nonessentials. The semiconductor circuit comprises an arithmetic circuit (adders 1-3) and delay means (memory 4). The arithmetic circuit includes arithmetic units for operation on input data, and they operate on digits of input data in a period of operation time, and produce results of operation, together with data corresponding to a carry, if any. The output from the arithmetic circuit is delayed by one period of operation time through the delay means.

摘要翻译： 提供了一种用于算术处理的半导体电路和运算处理方法，其可以通过抑制浪费处理来提高处理数据的速率并减小电路的面积。 提供了一种用于计算输入数据的计算单元，该计算单元在计算时间单位内计算输入数字数据，并输出表示通过计算获得的结果的计算结果，并且如果在计算中产生进位，则计算电路（ 用于输出表示该进位的进位数据的加法器1-3）和用于将来自计算电路的计算结果延迟一个计算时间单位的延迟装置（存储器4）。

公开(公告)号：EP0685807A4

公开(公告)日：1997-08-13

申请号：EP94907084

申请日：1994-02-22

申请人： SHIBATA TADASHI ,  OHMI TADAHIRO

发明人： SHIBATA TADASHI ,  OHMI TADAHIRO ,  KOTANI KOJI

IPC分类号： G06F7/04 ,  G06G7/60 ,  G06N3/063 ,  H03K19/21

CPC分类号： G06N3/0635

摘要： A semiconductor integrated circuit capable of effecting data matching at a high speed is provided by using a simple circuit. The semiconductor integrated circuit includes at least one first input terminal and at least one second input terminal to which a voltage signal is inputted, and at least one output terminal. A predetermined signal is produced at the output terminal when the difference between values expressed by the two signals inputted to the first and second input terminals becomes smaller than a predetermined value. The semiconductor integrated circuit of this invention contains at least two inverters constituted of neuron MOS transistors, and the two signals described above or signals obtained by applying predetermined processing to the two signals are inputted to at least one of the input gates of the inverters.

公开(公告)号：EP0578821A4

公开(公告)日：1996-01-10

申请号：EP92907111

申请日：1992-03-21

申请人： SHIBATA TADASHI ,  OHMI TADAHIRO

发明人： SHIBATA TADASHI ,  OHMI TADAHIRO

IPC分类号： G06F7/49 ,  G06F7/50 ,  G06F7/501 ,  G06N3/063 ,  G11C11/56 ,  G11C16/04 ,  G11C27/00 ,  H01L29/788 ,  H03K19/0944 ,  G06G7/60 ,  H01L29/66

CPC分类号： G06F7/5013 ,  G06F7/49 ,  G06F2207/482 ,  G06F2207/4826 ,  G06N3/0635 ,  G11C11/54 ,  G11C11/5621 ,  G11C16/0408 ,  G11C27/005 ,  G11C2211/5611 ,  H01L29/7881 ,  H03K19/0944

摘要： A semiconductor device by which a circuit having the same functions as those of the conventional circuits is realized with a very small number of elements, and complex logical functions can be designed simply, and further, its layout is also possible. A semiconductor device made up of at least one neuron MOS transistor having a gate electrode provided in a potentially floating state in a portion for isolating a source and drain region via a first insulation film, and plural control electrodes which are capacitively coupled to the floating gate electrode via a second insulation film, is characterized in that the first signal is inputted to a first control gate elctrode of the first neuron MOS transistor, the first signal is inputted to a first inverter comprising one or more stages, and the output of the first inverter is inputted to a second control gate electrode which is one of the plural control gate electrodes other than the first control gate electrode.

摘要翻译： 具有与常规电路相同功能的电路的半导体器件通过非常少量的元件实现，并且可以简单地设计复杂的逻辑功能，此外，其布局也是可能的。 一种由至少一个神经元MOS晶体管组成的半导体器件，所述至少一个神经元MOS晶体管具有通过第一绝缘膜隔离源极和漏极区域的部分中具有以潜在浮置状态设置的栅电极和多个控制电极，所述多个控制电极电容耦合到所述浮置栅极 电极经由第二绝缘膜，其特征在于，第一信号被输入到第一神经元MOS晶体管的第一控制栅电极，第一信号被输入到包括一级或多级的第一反相器，并且第一信号的输出 逆变器被输入到除了第一控制栅电极之外的多个控制栅电极之一的第二控制栅电极。

公开(公告)号：EP0653793A4

公开(公告)日：1997-03-19

申请号：EP93916243

申请日：1993-07-29

申请人： SHIBATA TADASHI ,  OHMI TADAHIRO

发明人： SHIBATA TADASHI ,  OHMI TADAHIRO

IPC分类号： H01L27/10 ,  G06N3/063 ,  H01L27/115 ,  H01L29/788 ,  H03K5/24 ,  H01L29/78

CPC分类号： G06N3/0635 ,  H01L27/115 ,  H01L29/788 ,  H03K5/2472

摘要： A semiconductor device of simple circuit capable of comparing the magnitudes of plural data at a high speed. This device has an inverter circuit group containing one or more inverter circuits formed by neuron MOS transistors; means for applying to a first input gate of the inverter circuit a first signal voltage which is common to the inverters belonging to the foregoing inverter circuit group; means for applying predetermined second signal voltage to one or more second input gates other than the first input gate of the inverter; and means for detecting the variation of the output voltage in at least one inverter circuit of the inverter circuit group due to the variation with time of either the first or the second signal voltage or both, and for applying positive feedback to given inverters of the inverter circuit group according to the detection.

公开(公告)号：EP0685806A4

公开(公告)日：1997-03-26

申请号：EP94907083

申请日：1994-02-22

申请人： SHIBATA TADASHI ,  OHMI TADAHIRO

发明人： SHIBATA TADASHI ,  OHMI TADAHIRO ,  YAMASHITA TAKEO

IPC分类号： G06F7/02 ,  G06F7/24 ,  G06G7/60 ,  G06N3/063 ,  G11C15/04 ,  H01L27/10 ,  H03K19/00 ,  H03K19/0948

CPC分类号： G06F7/24 ,  G06N3/0635

摘要： A device comprising invertor circuit group including two or more invertor circuits formed by neuron MOS transistors; means for applying a first signal voltage common to the two or more invertors of the invertor circuit group to a first input gate of the invertor circuits; means for applying a given second signal to one or more second input gates other than the first input gate of the invertor circuits; a delay circuit for transmitting the variation of the output voltage of at least one of the invertor circuits of the invertor circuit group with a time delay generated by use of the variation with time of the signal voltage of either or both of the first and second signal voltages; a transistor whose ON and OFF is controlled by the signal transmitted from the delay circuit; storage circuits taking in signals by the ON and OFF of the transistor; and means for executing a given logical operation with respect to the output voltage signals generated by the invertor circuit group. The device has a function of storing the result of the logical operation in the storage circuits.

公开(公告)号：EP0820030A4

公开(公告)日：1999-11-03

申请号：EP96907743

申请日：1996-04-01

申请人： SHIBATA TADASHI ,  OHMI TADAHIRO

发明人： SHIBATA TADASHI ,  OHMI TADAHIRO

IPC分类号： G06G7/26 ,  G06G7/12

CPC分类号： G06G7/26

摘要： A semiconductor operational circuit capable of instantaneously processing in parallel a large quantity of information. The semiconductor operational circuit executes a predetermined operation of a first signal train of signals A1, A2, ..., AN-1, AN comprising N signals and a second signal train of signals B1, B2, ..., BM-1, BM (where N and M are positive integers) comprising M signals. The circuit includes a plurality of first operational circuits for executing a predetermined operation of Ai and Bi+n (where i is a positive integer and n is an integer and 1

摘要翻译： 能够瞬时并行处理大量信息的半导体操作电路。 半导体操作电路执行包括N个信号和信号B1，B2，...，BM-1的第二信号序列的信号A1，A2，...，AN-1，AN的第一信号序列的预定操作， BM（其中N和M是正整数）包含M个信号。 该电路包括用于执行Ai和Bi + n的预定运算的多个第一运算电路（其中i是正整数，并且n是整数且1≤i≤N，1≤i+ n 生成输出信号Ci，n;至少一个第二运算电路，用于生成第一运算电路的一部分或全部输出信号的总和或由总和Sn确定的预定信号Tn 以及第三运算电路，用于找出多个不同的n值的值Sn或Tn，并确定给出Sn或Tn的最大值或最小值的n值。

公开(公告)号：EP0823684A4

公开(公告)日：1998-10-07

申请号：EP96907741

申请日：1996-04-01

申请人： SHIBATA TADASHI ,  OHMI TADAHIRO

发明人： SHIBATA TADASHI ,  OHMI TADAHIRO ,  YU NING MEI ,  NAKAI TSUTOMU

IPC分类号： G06F17/16 ,  G06J1/00 ,  G06K9/64 ,  G06F7/12

CPC分类号： G06K9/64 ,  G06F17/16 ,  G06J1/00

摘要： A semiconductor operational circuit capable of executing an operation of an analog vector at a high speed and highly accurately. The semiconductor operational circuit for executing a predetermined operation of a signal train of N signals A1, A2, ..., Ai, ..., AN. The circuit includes first means for generating an output signal M proportional to the sum of the signal train (A1 + A2 + ..., + Ai + ... + AN), second means for generating an output signal S proportional to the product of the sum by a predetermined weighting constant xi (x1A1 + x2A2 + ... + xiAi + ... + xNAN) and a circuit for calculating at least one fjM - gjS, using L sets of constants (f1, g1), (f2, g2), ..., (fj, gj), ..., (fL, gL) and generating an output signal having logic "1" or "0" in accordance with the results of this calculation.

公开(公告)号：EP0667588A4

公开(公告)日：1998-01-28

申请号：EP93923668

申请日：1993-10-29

申请人： SHIBATA TADASHI ,  OHMI TADAHIRO

发明人： SHIBATA TADASHI ,  OHMI TADAHIRO

IPC分类号： G06F15/18 ,  G06G7/60 ,  G06N3/063 ,  G06N99/00 ,  H01L21/822 ,  H01L27/04 ,  H01L29/78

CPC分类号： G06N3/0635

公开(公告)号：EP0657934A4

公开(公告)日：1997-09-03

申请号：EP93919578

申请日：1993-08-26

申请人： SHIBATA TADASHI ,  OHMI TADAHIRO

发明人： SHIBATA TADASHI ,  OHMI TADAHIRO

IPC分类号： H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H01L27/118 ,  H03K19/173 ,  H01L29/78

CPC分类号： H03K19/1736 ,  H01L27/11803

摘要： A semiconductor integrated circuit adaptable to any logic circuits using a common mask with the exception of a mask of metallic wirings so as to drastically improve performance of custom LSIs. The semiconductor integrated circuit comprises a logic circuit having a plurality of input terminals and at least one output terminal. The logic circuit includes a plurality of circuit blocks of the same circuit construction. Each of the circuit blocks has at least two stages of inverter formed by MOS semiconductor devices and at least one layer of a wiring pattern having a different pattern. The output signal of each block is defined by a predetermined function of an input signal.

摘要翻译： 一种半导体集成电路，适用于使用除了金属布线掩模之外的共用掩模的任何逻辑电路，从而大大提高定制LSI的性能。 半导体集成电路包括具有多个输入端和至少一个输出端的逻辑电路。 逻辑电路包括具有相同电路结构的多个电路块。 每个电路块具有由MOS半导体器件形成的至少两级的反相器和至少一层具有不同图案的布线图案。 每个块的输出信号由输入信号的预定功能定义。