Abstract:
A multicomponent dielectric film includes discrete overlapping dielectric layers of at least a first polymer material, a second polymer material, and a third polymer material. Adjoining dielectric layers define a generally planar interface therebetween which lies generally in an x-y plane of an x-y-z coordinate system. The interfaces between the layers delocalizing the charge build up in the layers. At least one dielectric layer including a stack of discrete polymer layers with polymer layer interfaces extending transverse to the x-y plane and optionally at least one filler having a higher dielectric constant than the first polymer material, the second polymer material, and/or the third polymer material.
Abstract:
In one embodiment, a system, comprising: a first non-magnetic conductive electrode; a second non-magnetic conductive electrode; a dielectric layer disposed between the first and second electrodes, the dielectric layer extending between the first and second electrodes; and first and second layers comprising plural pairs of magnetically coupled pairings of discrete magnets, the first and second layers separated by a non-magnetic material, wherein the magnets of at least the first layer are conductively connected to the first non-magnetic conductive electrode.
Abstract:
A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer.
Abstract:
In one or more embodiments, circuitry is provided for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The capacitive coupling is provided by one or more capacitive structures having a breakdown voltage that is defined by way of the various components and their spacing. The capacitive structures each include three capacitive plates arranged to have two plates located in an upper layer and one plate located in a lower layer. A communication signal can be transmitted via the capacitive coupling created between the lower plate and each of the upper plates, respectively.
Abstract:
The inventive supercapacitor comprises electrodes with a nanostructured material arranged therebetween, said material being consisted of clusters provided with tunnel-transparent shells. The cluster is dimensioned in such a way it enables an electron to exhibit the resonance properties within the range of 7.2517 nm ≤ r ≤ 29.0068 nm. Said dimensions are defined by the annular radius of the electron wave according to the formula Ro=/(meα2c)=7.2517 nm, where / is the Planck constant, m¿e? is the electron mass, α=1/137.036 is a fine structure constant, c is the light speed. The cluster dimension is pre-determined in the range from ro=7.2517 nm. Energy storage in the quantum supercapacitor is carried out by means of a controlled breakdown of the nanostructured dielectric material followed by the recovery thereof. Said energy is stored regularly through out the total volume of the nanostructured material as a result of a resonance pairing of electrons on the cluster. Specific energy stored in the capacitor is equal to 1.66 MJ/kg.
Abstract:
A capacitor (10) includes a planar electrode layer (12) which is mounted between a pair of dielectric layers (14, 16). The electrode layer (12) generally is centered with respect to the dielectric layers (14, 16), and one of the dielectric layers has a pair of spaced-apart leads (18, 20). The electrode layer (12) is buried within the dielectric layers (14, 16) on which the leads are mounted, and the leads (18, 20) allow the development of a selected value of capacitance between the leads (18, 20).
Abstract:
A ceramic substrate for hard disks, thin film chip capacitors, and hybrid ICs, of titanium oxide or aluminum oxide, has an extremely small number of pores of larger than 3 mu m diameter in the surface. The substrate is fabricated by burning finely powdered high-purity titanium oxide or high-purity aluminum oxide in the air, an inert atmosphere at 1,100-1,300 DEG C, or a reducing atmosphere at 1,200-1,400 DEG C and then, subjecting it to an HIP process.
Abstract:
A shielded low dielectric absorbtion capacitor (1) is produced using the capacitance between the center conductor (6) and outer shield of a length of coaxial cable (2) having a dielectric (5) made from TFE (Teflon).