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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权

    公开(公告)号：EP2056351B1

    公开(公告)日：2018-09-26

    申请号：EP08253585.7

    申请日：2008-10-31

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Takagi, Kazutaka

    IPC: H01L29/778 ,  H01L29/812 ,  H01L29/06 ,  H01L29/08 ,  H01L29/20 ,  H01L29/417

    CPC classification number: H01L29/7787 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/812 ,  H01L29/8124

    Abstract: A semiconductor device includes: a substrate region; a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of the substrate regions; an active area between gate and source placed between the gate electrode and the source electrode; an active area between gate and drain placed between the gate electrode and the drain electrode; an active area placed on the substrate region of the underneath part of the gate electrode, the source electrode, and the drain electrode; and a non-active area placed adjoining the active area, the active area between gate and source, and the active area between gate and drain. Furthermore, width W A1 of the active area between gate and source is wider than width W A2 of the active area between gate and drain. Channel resistance of an active area between source and gate placed between a gate electrode and a source electrode is reduced, and high-frequency performance is provided.

    Radio frequency semiconductor device package and method for manufacturing same, and radio frequency semiconductor device
    4.
    发明公开
    Radio frequency semiconductor device package and method for manufacturing same, and radio frequency semiconductor device 审中-公开
    Funkfrequenzhalbleitervorrichtungsverpackung und Herstellungsverfahrendafürsowie Funkfrequenzhalbleitervorrichtung

    公开(公告)号：EP2919264A1

    公开(公告)日：2015-09-16

    申请号：EP15157666.7

    申请日：2015-03-04

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Takagi, Kazutaka

    IPC: H01L23/047 ,  H01L23/10 ,  H01L23/66

    CPC classification number: H01L23/047 ,  B23K1/0016 ,  B23K1/20 ,  B23K35/3006 ,  H01L21/4817 ,  H01L23/06 ,  H01L23/10 ,  H01L23/66 ,  H01L2224/49175

    Abstract: A radio frequency semiconductor device package (5) includes a metal base plate (30), a first metal wall (10), a second metal wall (20), and feed-through parts (50). The first metal wall (10) is provided with first and second openings (10a) and connected onto the metal base plate (30). The first and second openings (10a) are set back from a lower surface side of the first metal wall (10) and do not reach an upper surface (10c) of the first metal wall (10). The second metal wall (20) is connected to the upper surface (10c) of the first metal wall (10). Thickness of the second metal wall (20) is larger than thickness of the first metal wall (10). The feed-through parts (50) include insulators and line patterns (54) insulated from the first and second metal walls and are joined to inner walls of the openings (10a) and the metal base plate (30).

    Abstract translation: 射频半导体器件封装（5）包括金属基板（30），第一金属壁（10），第二金属壁（20）和馈通部件（50）。 第一金属壁（10）设置有第一和第二开口（10a）并且连接到金属基板（30）上。 第一和第二开口（10a）从第一金属壁（10）的下表面侧放回，并且不到达第一金属壁（10）的上表面（10c）。 第二金属壁（20）连接到第一金属壁（10）的上表面（10c）。 第二金属壁（20）的厚度大于第一金属壁（10）的厚度。 馈通部分（50）包括与第一和第二金属壁绝缘的绝缘体和线图案（54），并且连接到开口（10a）和金属基板（30）的内​​壁。

    Semiconductor device
    5.
    发明公开
    Semiconductor device 有权
    半导体器件

    公开(公告)号：EP2447998A1

    公开(公告)日：2012-05-02

    申请号：EP11187955.7

    申请日：2008-10-24

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Takagi, Kazutaka

    IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/20 ,  H01L29/24 ,  H01L29/772

    CPC classification number: H01L29/41758 ,  H01L21/8213 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/0605 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/4238 ,  H01L29/772

    Abstract: A semiconductor device comprising: a substrate; a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of the substrate, and have a plurality of fingers, respectively; a gate terminal electrode, a source terminal electrode, and a drain terminal electrode which are placed on the first surface of the substrate, and ties a plurality of fingers, respectively for every the gate electrode, the source electrode, and the drain electrode; an active area placed on the substrate under the gate electrode, the source electrode, and the drain electrode; a non-active area placed on the substrate where the active area is not placed under the gate electrode, the source electrode, and the drain electrode; and a via hole connected to the source terminal electrode, wherein, the active area is divided in a manner of a stripe shape extended in a first direction, and the gate electrodes are formed as fishbone placement, and a gate bus line of the concerned fishbone placement is placed on the non-active area of the stripe shape between the active areas extended in the first direction, and each of a plurality of gate finger electrodes are connected to the gate bus line and the drain electrode is also formed as fishbone placement, and each of a plurality of the drain finger electrodes are connected to a drain bus line extended in the first direction and connected to the drain terminal electrode.

    Abstract translation: 一种半导体器件，包括：衬底; 栅电极，源电极和漏电极，所述栅电极，所述源电极和所述漏电极分别设置在所述基板的第一表面上并具有多个指状物; 栅极端子电极，源极端子电极和漏极端子电极，所述栅极端子电极，源极端子电极和漏极端子电极分别设置在所述基板的所述第一表面上，并且针对每个所述栅极电极，所述源极电极和所述漏极电极分别连接多个指状物; 在所述栅电极，所述源电极和所述漏电极之下的所述衬底上放置的有源区; 放置在衬底上的非有源区，其中有源区不放置在栅电极，源电极和漏电极下方; 以及与所述源极端子电极连接的过孔，所述有源区域在第一方向上以条状延伸，所述栅极电极形成为鱼骨的配置，所述鱼骨的栅极总线 在沿第一方向延伸的有源区域之间放置条形的非有源区域，并且多个栅极指状电极中的每一个都连接到栅极总线，并且漏极也形成为鱼骨放置， 并且多个漏极指状电极中的每一个连接到沿第一方向延伸并连接到漏极端子电极的漏极总线。

    Semiconductor device
    6.
    发明公开
    Semiconductor device 有权
    Halbleiterbauelement

    公开(公告)号：EP2288020A2

    公开(公告)日：2011-02-23

    申请号：EP10250900.7

    申请日：2010-05-10

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Ng, Choon Yong ,  Takagi, Kazutaka ,  Tomita, Naotaka

    IPC: H03F1/08 ,  H03F1/14

    CPC classification number: H03F1/086 ,  H03F1/14 ,  H03F3/193 ,  H03F3/211

    Abstract: According to one embodiment, there is a semiconductor device including a first active element, a second active element connected in parallel with the first active element, and a first stabilization circuit connected between a gate of the first active element and a gate of the second active element and configured with a parallel circuit of a gate bypass resistor, a gate bypass capacitor, and a gate bypass inductor, the first stabilization circuit having a resonant frequency equal to an odd mode resonant frequency.

    Abstract translation: 根据一个实施例，存在包括第一有源元件，与第一有源元件并联连接的第二有源元件的半导体器件，以及连接在第一有源元件的栅极和第二有源元件的栅极之间的第一稳定电路 元件，并配置有栅极旁路电阻器，栅极旁路电容器和栅极旁路电感器的并联电路，第一稳定电路具有等于奇数模式谐振频率的谐振频率。

    A high frequency semiconductor device
    7.
    发明公开
    A high frequency semiconductor device 审中-公开
    Hochfrequenzhalbleitervorrichtung

    公开(公告)号：EP2197030A2

    公开(公告)日：2010-06-16

    申请号：EP09252126.9

    申请日：2009-09-03

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Takagi, Kazutaka

    IPC: H01L23/66 ,  H03F1/56

    Abstract: A high frequency semiconductor device (25) includes: a field effect transistor (24) including gate terminal electrodes (G1-G10), source terminal electrodes (S1-S11), and a drain terminal electrode (D); an input circuit pattern (17) and an output circuit pattern (18) which are disposed adjoining of the field effect transistor; a plurality of input bonding wires (12,12L) configured to connect the plurality of the gate terminal electrodes (G1-G10) and the input circuit pattern (17); and a plurality of output bonding wires (14,14L) configured to connect the drain terminal electrode (D) and the output circuit pattern (18), whereby the input/output signal phase is matched by adjusting an inductance distribution of a plurality of input/output bonding wires, and whereby gain and output power is improved, and whereby an oscillation due to unbalanced operation of each FET cell is supressed.

    Abstract translation: 高频半导体器件（25）包括：包括栅极端子电极（G1-G10），源极端子电极（S1-S11）和漏极端子电极（D）的场效应晶体管（24） 输入电路图案（17）和与场效应晶体管相邻设置的输出电路图案（18）; 多个输入接合线（12,12L），被配置为连接多个栅极端子电极（G1-G10）和输入电路图案（17）; 以及多个输出接合线（14,14L），其被配置为连接所述漏极端子电极（D）和所述输出电路图案（18），由此所述输入/输出信号相位通过调整多个输入的电感分布来匹配 /输出接合线，从而提高增益和输出功率，并且由此抑制由于每个FET单元的不平衡操作引起的振荡。

    Semiconductor device and fabrication method of the semiconductor device
    8.
    发明公开
    Semiconductor device and fabrication method of the semiconductor device 有权
    半导体器件和半导体器件的制造方法

    公开(公告)号：EP2083442A1

    公开(公告)日：2009-07-29

    申请号：EP08253728.3

    申请日：2008-11-14

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Takagi, Kazutaka

    IPC: H01L23/482 ,  H01L23/04

    CPC classification number: H01L23/04 ,  H01L23/041 ,  H01L23/4824 ,  H01L2924/0002 ,  H01L2924/13063 ,  H01L2924/1423 ,  H01L2924/00

    Abstract: A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate, and have a plurality of fingers; a gate terminal electrode, a source terminal electrode, and the drain terminal electrode which governed and formed a plurality of fingers for every the gate electrode, the source electrode, and the drain electrode; an active area placed on an underneath part of the gate electrode, the source electrode, and the drain electrode, on the substrate between the gate electrode and source electrode, and on the substrate between the gate electrode and the drain electrode; a sealing layer which is placed on the active area, the gate electrode, the source electrode, and the drain electrode through a cavity part, and performs a hermetic seal of the active area, the gate electrode, the source electrode, and the drain electrode. Accordingly, the semiconductor element itself can have air-tightness, it is not necessary to cover the gate electrode surface with a damp-proof protective film, gate capacitance of the semiconductor element is reduced, and high frequency characteristics and gain of the semiconductor element improve.

    Abstract translation: 一种半导体器件和半导体器件的制造方法，所述半导体器件包括：栅电极，源电极和漏电极，放置在衬底的第一表面上并具有多个指状物; 栅极端子电极，源极端子电极和漏极端子电极，所述栅极端子电极，源极端子电极和漏极端子电极对于栅极电极，源极电极和漏极电极中的每一个支配并形成多个指状物; 位于所述栅电极和所述源电极之间的所述衬底上以及所述栅电极和所述漏电极之间的所述衬底上的放置在所述栅电极，所述源电极和所述漏电极的下方部分上的有源区; 密封层，通过空腔部分放置在有源区，栅电极，源电极和漏电极上，并且执行有源区，栅电极，源电极和漏电极的气密密封 。 因此，半导体元件本身可具有气密性，不需要用防潮保护膜覆盖栅电极表面，半导体元件的栅极电容减小，并且半导体元件的高频特性和增益提高 。

    Microwave semiconductor amplifier
    9.
    发明授权
    Microwave semiconductor amplifier 有权
    微波半导体放大器

    公开(公告)号：EP2637302B1

    公开(公告)日：2018-03-28

    申请号：EP12199817.3

    申请日：2012-12-31

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Takagi, Kazutaka

    IPC: H03F1/56 ,  H03F3/60 ,  H01L23/64

    CPC classification number: H03F3/04 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6655 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H03F1/565 ,  H03F3/60 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/423 ,  H01L2924/00

    Abstract: A microwave semiconductor amplifier includes a semiconductor amplifier element (14), an input matching circuit (12) and an output matching circuit (20). The semiconductor amplifying element (14) includes an input electrode and an output electrode and has a capacitive output impedance. The input matching circuit (12) is connected to the input electrode. The output matching circuit (20) includes a bonding wire (15) and a first transmission line (16). The bonding wire (15) includes first and second end portions. The first end portion is connected to the output electrode. The second end portion is connected to one end portion of the first transmission line (16). A fundamental impedance and a second harmonic impedance seen toward the external load change toward the one end portion. The second harmonic impedance at the one end portion has an inductive reactance. The output matching circuit (20) matches the capacitive output impedance of the semiconductor amplifying element (14) to the fundamental impedance of the external load.

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