公开(公告)号：EP3050091B1

公开(公告)日：2019-04-10

申请号：EP13894881.5

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： PILLARISETTY, Ravi ,  DASGUPTA, Sansaptak ,  GOEL, Niti ,  LE, Van H. ,  RADOSAVLJEVIC, Marko ,  DEWEY, Gilbert ,  MUKHERJEE, Niloy ,  METZ, Matthew V. ,  RACHMADY, Willy ,  KAVALIEROS, Jack T. ,  CHU-KUNG, Benjamin ,  KENNEL, Harold W. ,  CEA, Stephen M. ,  CHAU, Robert S.

IPC: H01L21/8234 ,  H01L29/267 ,  H01L29/165 ,  H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L29/20 ,  H01L29/16

公开(公告)号：EP3314659A1

公开(公告)日：2018-05-02

申请号：EP15896569.9

申请日：2015-06-26

Applicant: INTEL Corporation

Inventor： DASGUPTA, Sansaptak ,  THEN, Han Wui ,  RADOSAVLJEVIC, Marko ,  GARDNER, Sanaz K. ,  SUNG, Seung Hoon ,  CHAU, Robert S.

IPC: H01L29/778 ,  H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7786 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0445 ,  H01L21/8258 ,  H01L27/085 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/66462

Abstract: Crystalline heterostructures including an elevated crystalline structure extending from one or more trenches in a trench layer disposed over a crystalline substrate are described. In some embodiments, an interfacial layer is disposed over a silicon substrate surface. The interfacial layer facilitates growth of the elevated structure from a bottom of the trench at growth temperatures that may otherwise degrade the substrate surface and induce more defects in the elevated structure. The trench layer may be disposed over the interfacial layer with a trench bottom exposing a portion of the interfacial layer. Arbitrarily large merged crystal structures having low defect density surfaces may be overgrown from the trenches. Devices, such as III-N transistors, may be further formed on the raised crystalline structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate.

公开(公告)号：EP3120385A1

公开(公告)日：2017-01-25

申请号：EP14886535.5

申请日：2014-03-18

Applicant: Intel Corporation

Inventor： MUKHERJEE, Niloy ,  DOYLE, Brian S. ,  DASGUPTA, Sansaptak ,  RADOSAVLJEVIC, Marko ,  PILLARISETTY, Ravi ,  THEN, Han Wui ,  RAO, Valluri R. ,  CHAU, Robert S.

IPC: H01L29/04 ,  H01L21/763

CPC classification number: H01L21/02513 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02422 ,  H01L21/02428 ,  H01L21/02488 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02549 ,  H01L21/02551 ,  H01L21/02595 ,  H01L21/02631 ,  H01L21/02675 ,  H01L21/763 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/78603 ,  H01L29/78681

Abstract: Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a polycrystalline semiconductor material, and a polycrystalline dielectric disposed between and adjacent to the flexible substrate and the polycrystalline semiconductor material. The polycrystalline semiconductor material may include a polycrystalline III-V material, a polycrystalline II-VI material or polycrystalline germanium. Other embodiments may be disclosed and/or claimed.

Abstract translation: 本文公开了半导体组件的实施例以及相关的集成电路器件和技术。 在一些实施例中，半导体组件可以包括柔性衬底，多晶半导体材料以及设置在柔性衬底和多晶半导体材料之间和之间的多晶电介质。 多晶半导体材料。 多晶半导体材料可以包括多晶III-V材料，多晶II-VI材料或多晶锗。 可以公开和/或要求保护其他实施例。

公开(公告)号：EP3087612A1

公开(公告)日：2016-11-02

申请号：EP13900386.7

申请日：2013-12-23

Applicant: Intel Corporation

Inventor： THEN, Han Wui ,  CHAU, Robert S. ,  DASGUPTA, Sansaptak ,  RADOSAVLJEVIC, Marko ,  CHU-KUNG, Benjamin ,  SUNG, Seung Hoon Hoon ,  GARDNER, Sanaz K. ,  PILLARISETTY, Ravi

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/0605 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/32 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66795

Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.

Abstract translation: 技术是游离缺失盘用于形成在半导体衬底的GaN晶体管。 在半导体基片的顶部上的绝缘层的形式。 沟槽，填充有沟槽材料，其包含III-V族半导体材料，形成穿过绝缘层并延伸到所述半导体衬底。 一种信道结构，含有具有的缺陷密度比沟槽材料低的III-V材料，直接在绝缘层的顶部上且邻近于所述沟槽的形式。 的源极和所述信道结构的相对侧漏形式，并在信道结构的栅极形式。 所述半导体衬底形成一个平面时其中两个氮化镓晶体管和其它晶体管可以形成。

公开(公告)号：EP3050077A1

公开(公告)日：2016-08-03

申请号：EP13894184.4

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： DASGUPTA, Sansaptak ,  THEN, Han Wui ,  SUNG, Seung Hoon ,  GARDNER, Sanaz K. ,  RADOSAVLJEVIC, Marko ,  CHU-KUNG, Benjamin ,  CHAU, Robert S.

IPC: H01L21/20

CPC classification number: H01L21/0243 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/8258 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7787

Abstract: An insulating layer is conformally deposited on a plurality of mesa structures in a trench on a substrate. The insulating layer fills a space outside the mesa structures. A nucleation layer is deposited on the mesa structures. A III-V material layer is deposited on the nucleation layer. The III-V material layer is laterally grown over the insulating layer.

Abstract translation: 绝缘层被共形沉积在衬底上的沟槽中的多个台面结构上。 绝缘层填充台面结构外部的空间。 成核层沉积在台面结构上。 在成核层上沉积III-V材料层。 在绝缘层上横向生长III-V材料层。

公开(公告)号：EP2901472A1

公开(公告)日：2015-08-05

申请号：EP13840768.9

申请日：2013-06-20

Applicant: Intel Corporation

Inventor： PILLARISETTY, Ravi ,  SUNG, Seung Hoon ,  GOEL, Niti ,  KAVALIEROS, Jack T. ,  DASGUPTA, Sansaptak ,  LE, Van H. ,  RACHMADY, Willy ,  RADOSAVLJEVIC, Marko ,  DEWEY, Gilbert ,  THEN, Han Wui ,  MUKHERJEE, Niloy ,  METZ, Matthew V. ,  CHAU, Robert S.

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/20

CPC classification number: H01L21/845 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.

公开(公告)号：EP3688799A1

公开(公告)日：2020-08-05

申请号：EP17926938.6

申请日：2017-09-28

Applicant: INTEL Corporation

Inventor： THEN, Han Wui ,  RADOSAVLJEVIC, Marko ,  DASGUPTA, Sansaptak ,  TRONIC, Tristan A. ,  PAUL, Rajat K.

IPC: H01L23/525 ,  H01L23/62

公开(公告)号：EP3591691A1

公开(公告)日：2020-01-08

申请号：EP19175270.8

申请日：2019-05-17

Applicant: INTEL Corporation

Inventor： RADOSAVLJEVIC, Marko ,  THEN, Han Wui ,  DASGUPTA, Sansaptak ,  FISCHER, Paul

IPC: H01L21/336 ,  H01L29/778 ,  H01L29/423 ,  H01L29/08 ,  H01L29/20

Abstract: A transistor (100) includes a first part of a gate (111) above a substrate (101) that has a first width and a second part of the gate above the first part of the gate that is centered with respect to the first part of the gate and that has a second width that is greater than the first width. The first part of the gate and the second part of the gate form a single monolithic T-gate structure.

公开(公告)号：EP3313777A1

公开(公告)日：2018-05-02

申请号：EP15896550.9

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： THEN, Han Wui ,  DASGUPTA, Sansaptak ,  GARDNER, Sanaz K. ,  PILLARISETTY, Ravi ,  RADOSAVLJEVIC, Marko ,  SUNG, Seung Hoon ,  CHAU, Robert S.

IPC: B81B7/02 ,  B81C1/00 ,  H01L41/18 ,  H01L41/083

CPC classification number: B81C1/00246 ,  B81B3/0021 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C2203/0714 ,  G01L1/18

Abstract: Techniques are disclosed for forming group III material-nitride (III-N) microelectromechanical systems (MEMS) structures on a group IV substrate, such as a silicon, silicon germanium, or germanium substrate. In some cases, the techniques include forming a III-N layer on the substrate and optionally on shallow trench isolation (STI) material, and then releasing the III-N layer by etching to form a free portion of the III-N layer suspended over the substrate. The techniques may include, for example, using a wet etch process that selectively etches the substrate and/or STI material, but does not etch the III-N material (or etches the III-N material at a substantially slower rate). Piezoresistive elements can be formed on the III-N layer to, for example, detect vibrations or deflection in the free/suspended portion of the III-N layer. Accordingly, MEMS sensors can be formed using the techniques, such as accelerometers, gyroscopes, and pressure sensors, for example.

公开(公告)号：EP3221886A1

公开(公告)日：2017-09-27

申请号：EP14906448.7

申请日：2014-11-18

Applicant: Intel Corporation

Inventor： THEN, Han Wui ,  DASGUPTA, Sansaptak ,  RADOSAVLJEVIC, Marko ,  CHAU, Robert

IPC: H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/7786

Abstract: CMOS circuits may formed using p-channel gallium nitride transistors and n-channel gallium nitride transistors, wherein both the p-channel gallium nitride transistors and the n-channel gallium nitride transistors are formed on a single layered structure comprising a polarization layer deposited on a first gallium nitride layer and a second gallium nitride layer deposited on the polarization layer. Having both n-channel gallium nitride transistors and p-channel gallium nitride transistors s on the same layer structure may enable “all gallium nitride transistor” implementations of circuits including logic, digital, and analog circuitries spanning low supply voltages to high supply voltages.

Abstract translation: CMOS电路可以使用p沟道氮化镓晶体管和n沟道氮化镓晶体管来形成，其中p沟道氮化镓晶体管和n沟道氮化镓晶体管均形成在单层结构上，该单层结构包括沉积在 第一氮化镓层和沉积在偏振层上的第二氮化镓层。 具有n沟道氮化镓晶体管和p沟道氮化镓晶体管s在同一层结构上可以实现包括跨越低电源电压到高电源电压的逻辑，数字和模拟电路的电路的“所有氮化镓晶体管”实现。