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    SEMICONDUCTOR STRUCTURE AND LAYOUT THEREOF, AND SEMICONDUCTOR DEVICE
    2.
    发明公开
    SEMICONDUCTOR STRUCTURE AND LAYOUT THEREOF, AND SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：EP4156187A1

    公开(公告)日：2023-03-29

    申请号：EP21916637.8

    申请日：2021-09-18

    申请人： Changxin Memory Technologies, Inc.

    发明人： WANG, Peihuan

    IPC分类号： G11C11/4063 ,  H01L27/108

    摘要： The disclosure provides a semiconductor structure, a layout of the semiconductor structure and a semiconductor device. The semiconductor structure includes: a plurality of first conductive layers that are spaced; a plurality of capacitor banks, and the capacitor bank being on the first conductive layer in one-to-one correspondence and the capacitor bank including at least a capacitor, each capacitor including a lower electrode layer, a capacitance dielectric layer and an upper electrode layer stacked from bottom to top; a capacitor plate, wherein the capacitor plate is on each upper electrode layer; and a second conductive layer, wherein the second conductive layer is above the capacitor plate and connected with the capacitor plate. In the above semiconductor structure, the second conductive layer is formed above the capacitor plate, and the second conductive layer is connected with the capacitor plate, so that in the semiconductor structure, the second conductive layer is equivalent to being connected in parallel at two ends of the capacitor plate, that is, the second conductive layer is connected with the capacitor plate in parallel, and the resistance formed by the parallel connection of the second conductive layer and the capacitor plate is lower than the resistance of the capacitor plate itself, thereby avoiding the problem of affecting the performance due to the high resistance and improving the performance of the semiconductor structure.

    METHOD, SYSTEM AND APPARATUS FOR TRI-STATING UNUSED DATA BYTES DURING DDR DRAM WRITES
    8.
    发明公开
    METHOD, SYSTEM AND APPARATUS FOR TRI-STATING UNUSED DATA BYTES DURING DDR DRAM WRITES 有权
    方法，系统和设备三态没用的字节时的DDR DRAM写入过程

    公开(公告)号：EP2368246A4

    公开(公告)日：2012-07-04

    申请号：EP09827078

    申请日：2009-11-17

    申请人： ATI TECHNOLOGIES ULC

    发明人： FRY JAMES ,  GUTHRIE GEORGE

    IPC分类号： G11C7/10 ,  G11C8/18 ,  G11C11/4063 ,  G11C11/4096

    CPC分类号： G11C7/1051 ,  G06F13/1668 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4096

    摘要： A memory interface circuit includes a plurality of data bus drivers and logic adapted to be operatively responsive to write driver mask information. If desired, the plurality of bus drivers and the logic may be implemented in separate integrated circuits. The plurality of bus drivers are adapted to be responsive to a write operation. The logic is also adapted to disable any one of the plurality of data bus drivers based on the write driver mask information during the write operation.

    摘要翻译： 存储器接口电路包括数据总线驱动器和逻辑angepasst的多元性可操作性地响应于写驱动器掩码信息。 如果需要清除，总线驱动器的多元性和逻辑可以在单独的集成电路来实施。 公交车司机的多元化是angepasst为响应写操作。 的逻辑是这样angepasst禁用基于所述写操作期间，写驱动器掩模信息数据总线驱动器的所述多个的任何一个。

    Semiconductor integrated circuit having low power consumption with self-refresh
    10.
    发明公开
    Semiconductor integrated circuit having low power consumption with self-refresh 有权
    在einen Halbleiter integrierte Schaltung mit niedrigem Stromverbrauch und Self-Refresh

    公开(公告)号：EP2395511A2

    公开(公告)日：2011-12-14

    申请号：EP11007385.5

    申请日：2006-11-30

    申请人： MOSAID Technologies Incorporated

    发明人： Oh, HakJune

    IPC分类号： G11C11/4063 ,  G11C8/10

    CPC分类号： G11C11/406 ,  G11C8/10

    摘要： A dynamic random access memory has logically identical circuits for providing the same logical control signals. Each set of control signals can have different electrical parameters. One circuit can be optimized for high speed performance, while another circuit can be optimized for low power consumption. The logically identical circuits can include wordline address predecoder circuits (400,402,404), where a high speed predecoder circuit (402) is enabled during a normal operating mode and a slower low power predecoder circuit (404) is enabled for self-refresh operations. During self-refresh operations, the high speed circuit (402) can be decoupled from the power supply to minimize its current leakage.

    摘要翻译： 动态随机存取存储器具有逻辑相同的电路，用于提供相同的逻辑控制信号。 每组控制信号可以具有不同的电参数。 一个电路可以针对高速性能进行优化，而另一个电路可以针对低功耗进行优化。 逻辑上相同的电路可以包括字线地址预解码器电路（400,402,404），其中高速预解码器电路（402）在正常操作模式期间被使能，并且较慢的低功率预解码器电路（404）被启用用于自刷新操作。 在自刷新操作期间，高速电路（402）可以与电源分离，以最小化其电流泄漏。