公开(公告)号：EP3258469B1

公开(公告)日：2021-10-06

申请号：EP17184129.9

申请日：2014-01-31

发明人： NG, Boon Bing ,  GOY, Hang Ru

IPC分类号： G11C16/08 ,  G11C16/10 ,  G11C8/04 ,  G11C8/12

公开(公告)号：EP3859535A1

公开(公告)日：2021-08-04

申请号：EP21153708.9

申请日：2021-01-27

申请人： STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

发明人： CHAWLA, Nitin ,  BOESCH, Thomas ,  GROVER, Anuj ,  SINGH, Surinder Pal ,  DESOLI, Giuseppe

IPC分类号： G06F12/02 ,  G11C11/22 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/419 ,  G11C7/10 ,  G11C8/04 ,  G11C8/08 ,  G11C8/10 ,  G11C11/54 ,  G06N3/04 ,  G06N3/063

摘要： A system includes a random access memory organized into indivudally addressable words. Streaming access control circuitry is coupled to word lines of the random access memory. The streaming access control circuitry responds to a request to access a plurality of individually addressable words of a determined region of the random access memory by generating control signals to drive the word lines to streamingly access the plurality of individually addressable words of the determined region. The request indicates an offset associated with the determined region and a pattern associated with the streaming access.

公开(公告)号：EP2727114B1

公开(公告)日：2020-04-22

申请号：EP11868835.7

申请日：2011-06-28

申请人： Hewlett Packard Enterprise Development LP

发明人： KELLY, Terrence, P. ,  DAVIS, Alan, L. ,  PICKETT, Matthew, D.

IPC分类号： G11C19/00 ,  G11C19/28 ,  G11C8/04 ,  G11C8/10 ,  G11C8/12 ,  G11C7/10

公开(公告)号：EP3579235A1

公开(公告)日：2019-12-11

申请号：EP19174519.9

申请日：2019-05-14

申请人： Samsung Electronics Co., Ltd.

发明人： OH, Eun-chu ,  KIM, Moo-sung ,  KIM, Young-sik ,  LEE, Yong-jun ,  Jeong-ho, LEE

IPC分类号： G11C13/00 ,  G11C5/02 ,  G11C8/04 ,  G11C8/14 ,  G11C11/16 ,  G06F12/02 ,  G06F12/06 ,  G11C29/00 ,  G11C29/52

摘要： Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER.

公开(公告)号：EP3266024A1

公开(公告)日：2018-01-10

申请号：EP16711404.0

申请日：2016-02-26

申请人： Northrop Grumman Systems Corporation

发明人： REOHR, William Robert ,  SHAUCK, Steven Brian ,  MILLER, Donald Lynn ,  HORNER, Jeremy William ,  JOSEPHSEN, Nathan Trent

IPC分类号： G11C11/44 ,  G11C7/22 ,  G11C7/12 ,  H01F6/00 ,  G11C8/04 ,  G11C8/18 ,  H01L39/22

CPC分类号： G11C11/44 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y25/00 ,  G11C7/12 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1693 ,  G11C19/32

摘要： One embodiment describes a quantum memory system. The system includes a plurality of quantum memory cells arranged in an array of rows and columns. Each of the plurality of quantum memory cells can be configured to store a binary logic state in response to write currents in a write operation and configured to provide an indication of the binary logic state in response to read currents in a read operation. The system also includes an array controller comprising a plurality of flux pumps configured to provide the write currents and the read currents with respect to the rows and columns. The array controller can be configured to control timing associated with the write operation and the read operation in response to memory request signals based on application of the write currents and the read currents and based on recharging flux associated with the plurality of flux pumps.

公开(公告)号：EP2467852A1

公开(公告)日：2012-06-27

申请号：EP10810321.9

申请日：2010-06-17

申请人： Rambus Inc.

发明人： SHEFFLER, Thomas ,  LAI, Lawrence ,  PENG, Liang ,  RYCHLIK, Bohuslav

IPC分类号： G11C8/04 ,  G11C7/10 ,  G11C7/22

CPC分类号： G06F12/023 ,  G06F2212/2024 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/22 ,  G11C8/10 ,  G11C2207/107 ,  H05K999/99

摘要： A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

公开(公告)号：EP2332143A4

公开(公告)日：2012-03-28

申请号：EP09819740

申请日：2009-10-06

申请人： MICRON TECHNOLOGY INC

发明人： KEETH BRENT ,  MARTIN CHRIS G ,  MANNING TROY A ,  JEDDELOH JOE M ,  COWLES TIMOTHY B ,  REHMEYER JIM ,  LABERGE PAUL A

IPC分类号： G11C8/04 ,  G11C8/06

CPC分类号： G06F12/08 ,  G06F12/10 ,  G11C5/025 ,  G11C29/04 ,  G11C29/18 ,  G11C29/76 ,  G11C29/78 ,  G11C29/808 ,  G11C29/812 ,  G11C29/883 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599

摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.

公开(公告)号：EP2330594A1

公开(公告)日：2011-06-08

申请号：EP10290278.0

申请日：2010-05-26

申请人： Crocus Technology S.A.

发明人： Berger, Neal ,  El Baraji, Mourad

IPC分类号： G11C8/04 ,  G11C11/56 ,  G11C19/02

CPC分类号： G11C19/08 ,  G11C8/04 ,  G11C11/1675 ,  G11C14/0081 ,  G11C19/02

摘要： The present disclosures concerns a register cell (1) comprising a differential amplifying portion (2) containing a first inverter (3) coupled to a second inverter (3') such as to form an unbalanced flip-flop circuit; a first and second bit line (BL0, BL1) connected to one end of the first and second inverter (3, 3'), respectively; and a first and second source line (SL0, SL1) connected to the other end of the first and second inverter (3, 3'), respectively; characterized by the register cell (1) further comprising a first and second magnetic tunnel junction (6, 6') electrically connected to the other end of the first and second inverter (3, 3'), respectively. The shift register disclosed herein can be made smaller than conventional shift registers and power consumption during the write and read operation of the shift registers can be low. The shift register disclosed herein can be made smaller than conventional shift registers and power consumption during the write and read operation of the shift registers can be low.

摘要翻译： 本公开涉及一种寄存器单元（1），包括：差分放大部分（2），包含耦合到第二反相器（3'）的第一反相器（3），以形成不平衡触发器电路; 分别连接到第一和第二逆变器（3,3'）的一端的第一和第二位线（BL0，BL1） 以及分别连接到第一和第二逆变器（3,3'）的另一端的第一和第二源极线（SL0，SL1） 其特征在于寄存器单元（1）还包括分别电连接到第一和第二逆变器（3,3'）的另一端的第一和第二磁性隧道结（6,6'）。 这里公开的移位寄存器可以比传统的移位寄存器小，并且在移位寄存器的写入和读取操作期间的功耗可能很低。 这里公开的移位寄存器可以比传统的移位寄存器小，并且在移位寄存器的写入和读取操作期间的功耗可能很低。

公开(公告)号：EP1830241B1

公开(公告)日：2008-06-25

申请号：EP06125958.6

申请日：1991-04-16

申请人： RAMBUS INC.

发明人： Farmwald, Michael ,  Horowitz, Mark

IPC分类号： G06F1/04 ,  G06F1/12 ,  G06F13/00 ,  G06F13/16 ,  G06F13/36 ,  G06F13/38 ,  G11C7/00 ,  G11C8/00 ,  G11C8/04

CPC分类号： G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16, 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices (15, 16 or 17), where the control information includes device-select information and the bus (18) has substantially fewer bus lines than the number of bits in a single address, and the bus (18) carries device-select information without the need for separated device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus (18) and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices (15, 16, 17). The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an Address Valid bus line carry address, data and control information for memory addresses up to 40 bits wide.

公开(公告)号：EP1217629B1

公开(公告)日：2007-07-25

申请号：EP01403322.9

申请日：2001-12-20

申请人： CHAUVIN ARNOUX

发明人： Arnoux, Daniel

IPC分类号： G11C27/02 ,  G11C8/04

CPC分类号： G11C8/04 ,  G11C27/02 ,  G11C27/024