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148 条记录 (耗时 0.023 秒)

    SEMICONDUCTOR DEVICES
    1.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：EP4462473A1

    公开(公告)日：2024-11-13

    申请号：EP24174723.7

    申请日：2024-05-08

    申请人： Samsung Electronics Co., Ltd.

    发明人： KIM, Heesub ,  JO, Gunho ,  KIM, Bomi ,  CHO, Eunho

    IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/48 ,  H01L23/528 ,  H01L23/535 ,  H01L27/118 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

    摘要： A semiconductor device (100) includes a substrate (101) having active regions (105) extending in a first direction (x), a device isolation layer (110) in the substrate (101) between the active regions (105) and exposing upper surfaces of the active regions (105), gate structures (160) on the active regions, intersecting the active regions and extending in a second direction (y), source/drain regions (150) adjacent to the gate structure (160) and on the active region (105), contact plugs (170) on the source/drain region (150), the contact plugs extending into respective recesses in the source/drain regions and electrically connected to the source/drain regions (150), a first power structure (VS1) between adjacent source/drain region (150) in the second direction (y) and electrically connected to at least one of the contact plugs (170), and a second power structure (VS2) penetrating the substrate (101) and on a lower end of the first power structure (VS1), and a lateral dielectric layer (155) on surfaces of the source/drain regions (105) and extending along an upper surface of the device isolation layer (110) and on a first portion of a side surface of the first power structure (VS1). The first power structure (VS1) has a first width (W1) at an upper thereof and a second width (W2) at the lower end thereof, the second width being equal to or greater than the first width.

    INTEGRATED CIRCUIT DEVICE
    4.
    发明公开
    INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：EP4407669A1

    公开(公告)日：2024-07-31

    申请号：EP24154349.5

    申请日：2024-01-29

    申请人： Samsung Electronics Co., Ltd.

    发明人： HWANG, Donghoon ,  HWANG, Inchan ,  KIM, Hyojin

    IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/535 ,  H01L29/423

    CPC分类号： H01L23/5286 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/535 ,  H01L29/42392

    摘要： An integrated circuit device is provided. The device includes: lower source/drain areas; lower contacts respectively on bottom surfaces of the lower source/drain areas; upper source/drain areas spaced apart from the lower source/drain areas in a vertical direction; upper contacts respectively on upper surfaces of the upper source/drain areas; and a first vertical conductive rail electrically connected to a first contact of the lower contacts and the upper contacts, the first vertical conductive rail extending in the vertical direction, and including a first portion having a first upper surface at a first vertical level and a second portion having a second upper surface at a second vertical level lower than the first vertical level. The second portion overlaps a first upper contact among the upper contacts in the vertical direction.

    INTEGRATED CIRCUIT CHIPS COMPRISING FORKSHEET DEVICES CONNECTED WITH BURIED POWER RAILS
    6.
    发明公开
    INTEGRATED CIRCUIT CHIPS COMPRISING FORKSHEET DEVICES CONNECTED WITH BURIED POWER RAILS 审中-公开

    公开(公告)号：EP4391032A1

    公开(公告)日：2024-06-26

    申请号：EP22216298.4

    申请日：2022-12-23

    申请人： Imec VZW

    发明人： CHAN, Boon Teik ,  HIBLOT, Gaspard ,  MIRABELLI, Gioele

    IPC分类号： H01L21/768 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L29/775

    CPC分类号： H01L29/775 ,  H01L21/76897 ,  H01L23/5286 ,  H01L23/535 ,  H01L21/823481 ,  H01L21/823475

    摘要： A method comprising providing (901) a semiconductor substrate, forming (902) a device layer (2) comprising a forksheet device (30) on the substrate and providing the substrate (1) with a substrate part (31) of a dielectric wall (3) of the forksheet device (30), a first shallow trench isolation (41) and a second shallow trench isolation (42), wherein an extending part (411) of the first shallow trench isolation (41) comprises a first surface (410) facing a second surface (420) of an extending part (421) of the second shallow trench isolation (42), wherein a region (100) between the first surface (410) and the second surface (420) comprises a substrate material (120), and a via (51), filled with a via material (510), contacting a source or drain contact (21) and extending into the substrate (1) between the first shallow trench isolation (41) and the dielectric wall (3), then removing (903) the substrate material (120) so as to expose an end (311) of the dielectric wall (3), the first surface (410), and the second surface (420), then obtaining (904) a first spacer (61) and a second spacer (62), so as to obtain a trench (122), wherein the end of the dielectric wall (3) is exposed to the trench (122), then depositing (905) an electrically insulating material in the trench (122) so as to form an extension (7).

    INTEGRATED CIRCUIT STRUCTURE WITH RECESSED SELF-ALIGNED DEEP BOUNDARY VIA
    7.
    发明公开
    INTEGRATED CIRCUIT STRUCTURE WITH RECESSED SELF-ALIGNED DEEP BOUNDARY VIA 审中-公开

    公开(公告)号：EP4300558A1

    公开(公告)日：2024-01-03

    申请号：EP23172259.6

    申请日：2023-05-09

    申请人： INTEL Corporation

    发明人： HARAN, Mohit ,  YEMENICIOGLU, Sukru ,  PATEL, Pratik ,  WALLACE, Charles H. ,  GULER, Leonard P. ,  PULS, Conor P. ,  ABD EL QADER, Makram ,  GHANI, Tahir

    IPC分类号： H01L21/74 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535

    摘要： Integrated circuit structures having recessed self-aligned deep boundary vias are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extends over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A backside metal routing layer is extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. The conductive structure includes a pillar portion in contact with the one of the one or more of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

    METAL-SEMICONDUCTOR JUNCTION FORMED BY A BURIED POWER RAIL
    8.
    发明公开
    METAL-SEMICONDUCTOR JUNCTION FORMED BY A BURIED POWER RAIL 审中-公开

    公开(公告)号：EP4210101A3

    公开(公告)日：2023-11-08

    申请号：EP22206295.2

    申请日：2022-11-09

    申请人： INTEL Corporation

    发明人： GEIGER, Richard ,  Panagopoulos, Georgios ,  Rauh, Johannes ,  Gossner, Harald

    IPC分类号： H01L23/528 ,  H01L21/74 ,  H01L21/768 ,  H01L23/535 ,  H01L27/02 ,  H01L27/092

    摘要： IC devices including IC devices including BPRs that form metal-semiconductor junctions with semiconductor sections where the BPRs are partially buried are disclosed. An example IC device includes a first layer comprising semiconductor structures, such as fins, nanowires, or nanoribbons. The IC device also includes a layer comprising an electrically conductive material and coupled to the semiconductor structures. The IC device further includes a support structure comprising a BPR and a semiconductor section. The BPR contacts with the semiconductor section and forms a metal-semiconductor junction. The metal-semiconductor junction constitutes a Schottky barrier for electrons. The IC device may include a SCR including a sequence of p-well, n-well, p-well, and n-well with Schottky barriers in the first p-well and the second n-well. The Schottky barrier may also be used as a guard ring to extract injected charge carriers.

    SELF-ALIGNED LATERAL CONTACTS
    10.
    发明公开
    SELF-ALIGNED LATERAL CONTACTS 审中-公开

    公开(公告)号：EP4125117A1

    公开(公告)日：2023-02-01

    申请号：EP22159400.5

    申请日：2022-03-01

    申请人： Intel Corporation

    发明人： Wei, Andy ,  Cheng, Yang-Chun ,  Chowdhury, Shaestagir ,  Bouche, Guillaume

    IPC分类号： H01L21/74 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L21/8238

    摘要： Techniques to form self-aligned lateral contacts. In an example, a first trench contact contacts a source or drain region of a transistor. A second trench contact includes non-contiguous first and second portions, each portion having a top surface that is co-planar with a top surface of the first trench contact as well as a top surface of the gate structure. A sidewall of the second trench contact is self-aligned to, and interfaces with, a sidewall of the first trench contact. A via extends from the first portion of the second trench contact to an underlying power rail. In some cases, the second portion of the second trench contact extends over a source or drain region of another transistor, without contacting that source or drain region. The fly-over portion of the second trench contact has a maximum height that is shorter than a maximum height of the first trench contact.