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    Load drive control device
    93.
    发明专利
    Load drive control device 有权
    负载驱动控制装置

    公开(公告)号：JP2014160928A

    公开(公告)日：2014-09-04

    申请号：JP2013030381

    申请日：2013-02-19

    Applicant: Hitachi Automotive Systems Ltd ,  日立オートモティブシステムズ株式会社

    Inventor： WATABE MITSUHIKO ,  KOYAMA KATSUYA ,  KURIMOTO YUJI ,  ISHIDA RYOSUKE

    IPC: H03K17/08 ,  H02M3/155 ,  H03K17/16 ,  H03K17/687

    CPC classification number: H02M3/158 ,  H02M2001/327 ,  H03K17/145 ,  H03K17/162

    Abstract: PROBLEM TO BE SOLVED: To provide a load drive control device that can keep on driving a load as long as possible.SOLUTION: A first gate drive section 33 supplies gates of first switching elements 35, 37 with first gate driving currents indicating charging/discharge currents to/from the gates of the first switching elements 35, 37, to drive the gates of the first switching elements 35, 37. A first slope variation circuit 16increases the first gate driving currents by a unit amount when an ambient temperature of the first switching elements 35, 37 is equal to or higher than a threshold H1, and decreases the first gate driving currents by a unit amount when the ambient temperature of the first switching elements 35, 37 is equal to or lower than a threshold L1.

    Abstract translation: 要解决的问题：提供一种可以尽可能长时间地保持负载驱动的负载驱动控制装置。解决方案：第一栅极驱动部分33向第一开关元件35,37的栅极提供指示充电/放电的第一栅极驱动电流 来自第一开关元件35,37的栅极的电流，以驱动第一开关元件35,37的栅极。第一斜率变化电路16当第一开关元件35,37的环境温度为第一栅极驱动电流时，将第一栅极驱动电流增加单位量 开关元件35,37等于或高于阈值H1，并且当第一开关元件35,37的环境温度等于或低于阈值L1时，第一栅极驱动电流减小单位量。

    Compensation-type current cell in order to scale the switching glitch in the digital / analog converter
    95.
    发明专利
    Compensation-type current cell in order to scale the switching glitch in the digital / analog converter 审中-公开

    公开(公告)号：JP2014513908A

    公开(公告)日：2014-06-05

    申请号：JP2014511603

    申请日：2012-05-18

    Applicant: クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： マクゴワン、ミヒャエル・ジョセフ

    IPC: H03K17/16 ,  H03K17/687 ,  H03M1/08 ,  H03M1/74

    CPC classification number: H03K17/162 ,  H03M1/0863 ,  H03M1/742

    Abstract: デジタル／アナログ変換器においてスイッチンググリッチを基準化するための補償型電流セル。 それぞれ第１および第２の入力信号に基づいて第１および第２の出力との間で入力電流をスイッチングするように構成された第１および第２のスイッチングトランジスタと、第２の出力に接続された第１の補償型電流を提供するために第１の入力信号に接続された第１の補償型トランジスタと、第１の出力に接続された第２の補償型電流を提供するために第２の入力信号に接続された第２の補償型トランジスタとを含み、ここで、第１および第２の補償型トランジスタは、互いに接続されたソース端子を有する、補償型電流セルが開示される。 別の態様において、スイッチンググリッチは、スイッチングトランジスタと補償型トランジスタとの間のサイズの差分に基づいて基準化される。

    Switch drive circuit
    96.
    发明专利
    Switch drive circuit 有权
    开关驱动电路

    公开(公告)号：JP2014103485A

    公开(公告)日：2014-06-05

    申请号：JP2012253022

    申请日：2012-11-19

    Applicant: Rohm Co Ltd ,  ローム株式会社

    Inventor： HATTORI TAKUYA

    IPC: H03K17/16 ,  H02M1/08 ,  H03K17/687

    CPC classification number: H02P6/14 ,  H02M1/08 ,  H02M1/38 ,  H03K5/133 ,  H03K5/1515 ,  H03K17/00 ,  H03K17/162 ,  H03K2005/00071

    Abstract: PROBLEM TO BE SOLVED: To set an appropriate dead time.SOLUTION: A switch drive circuit 20 includes: a switch signal generation section 23 for generating switch signals S1 and S2 to complementarily turn on/off switches 11 and 12 connected in series between an end of application of an input voltage Vi and an end of application of a ground voltage GND; driver sections 21 and 22 for generating gate signals G1 and G2 in response to the input of the switch signals S1 and S2; and a dead time setting section 24 for setting dead times Td1 and Td2 to keep both switches 11 and 12 off. At least either of the driver sections 21 and 22 includes a slew rate setting section for varying a slew rate of the gate signals G1, G2 according to a slew rate setting signal Sc. The dead time setting section 24 controllingly varies at least either of the dead times Td1 and Td2 according to at least either of the slew rate setting signal Sc and the input voltage Vi.

    Abstract translation: 要解决的问题：设置适当的死区时间。解决方案：开关驱动电路20包括：开关信号产生部23，用于产生开关信号S1和S2，以互补地接通/断开开关11和12，串联连接在端部 施加输入电压Vi和施加接地电压GND的结束; 用于响应于开关信号S1和S2的输入而产生门信号G1和G2的驱动器部分21和22; 以及用于设定死区时间Td1和Td2以使两个开关11和12关闭的死区时间设定部分24。 驱动器部分21和22中的至少任一个包括用于根据转换速率设置信号Sc改变门信号G1，G2的转换速率的转换速率设置部分。 死区时间设定部分24根据压摆率设定信号Sc和输入电压Vi中的至少一个来控​​制死区时间Td1和Td2中的至少一个。

    Semiconductor integrated circuit and power supply circuit
    97.
    发明专利
    Semiconductor integrated circuit and power supply circuit 有权
    半导体集成电路和电源电路

    公开(公告)号：JP2014036489A

    公开(公告)日：2014-02-24

    申请号：JP2012175884

    申请日：2012-08-08

    Applicant: Fujitsu Ltd ,  富士通株式会社

    Inventor： SAKAI YASUBUMI

    IPC: H02M3/145

    CPC classification number: H02M3/156 ,  G05F1/44 ,  H01L21/823493 ,  H01L27/0629 ,  H01L27/0727 ,  H02M1/08 ,  H02M3/1588 ,  H03K17/162 ,  H03K2217/0018 ,  H03K2217/0063 ,  Y02B70/1466

    Abstract: PROBLEM TO BE SOLVED: To inhibit capacity decline of a capacitor caused by parasitic capacitance of a semiconductor element.SOLUTION: In a voltage lower control circuit 10 which forms a DC-DC converter 16 provided in an IC 12, an end of a capacitor 36 for bootstrap is connected to an LX node 26A and the other end of the capacitor 36 is connected to a node 38B having higher potential than the LX node. In a transistor Ma, an N well 44 formed on a Psub is connected to the node 38B, and a P well 46 formed in the N well and a source S formed in the P well are connected to the LX node. With this configuration, parasitic capacitance between the N well and the P well of the transistor functions as electrostatic capacitance for bootstrap thereby to inhibit capacity decline of the electrostatic capacitance for bootstrap.

    Abstract translation: 要解决的问题：抑制由半导体元件的寄生电容引起的电容器的容量下降。解决方案：在形成设置在IC 12中的DC-DC转换器16的电压下控制电路10中，电容器36的一端 用于自举连接到LX节点26A，并且电容器36的另一端连接到具有比LX节点更高的电位的节点38B。 在晶体管Ma中，形成在Psub上的N阱44连接到节点38B，形成在N阱中的P阱46和形成在P阱中的源极S连接到LX节点。 通过这种配置，晶体管的N阱和P阱之间的寄生电容用作自举的静电电容，从而抑制用于引导的静电电容的容量下降。

    Method and apparatus used when tuning the capacitor digitally in an integrated circuit element
    98.
    发明专利
    Method and apparatus used when tuning the capacitor digitally in an integrated circuit element 有权
    空值

    公开(公告)号：JP5417346B2

    公开(公告)日：2014-02-12

    申请号：JP2010548750

    申请日：2009-03-02

    Applicant: ペレグリン セミコンダクター コーポレーション

    Inventor： ランタ，テロ，タピオ

    IPC: H01L21/822 ,  H01L27/04

    CPC classification number: H03H11/28 ,  H01F21/12 ,  H01G4/002 ,  H01G7/00 ,  H01L23/5223 ,  H01L27/0629 ,  H01L27/1203 ,  H01L28/60 ,  H03H7/0153 ,  H03H7/38 ,  H03J3/20 ,  H03J2200/10 ,  H03K17/162 ,  H03K17/687 ,  H03M1/1061 ,  H03M1/804

    Abstract: A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF- terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB. Each significant bit of the digital control word is coupled to corresponding and associated significant bit sub-circuits of the DTC, and thereby controls switching operation of the associated sub-circuit. DTCs are implemented using unit cells, wherein the LSB sub-circuit comprises a single unit cell. Next significant bit sub-circuits comprise x instantiations of the number of unit cells used to implement its associated and corresponding previous significant bit sub-circuit, wherein the value x is dependent upon a weighting coding used to weight the significant bit sub-circuits of the DTC. DTCs may be weighted in accordance with a binary code, thermometer code, a combination of the two, or any other convenient and useful code. In many embodiments, the unit cell comprises a plurality of stacked FETs in series with a capacitor. The unit cell may also include a plurality of gate resistors R G coupled to the gates of the stacked FETs, and a plurality of R DS resistors coupled across the drain and source of the stacked FETs. The stacked FETs improve the power handling capabilities of the DTC, allowing it meet or exceed high power handling requirements imposed by current and future communication standards.

    Abstract translation: 描述了用于集成电路器件中的电容器的数字调谐中使用的方法和装置。 描述了数字调谐电容器DTC，其有助于数字控制施加在第一和第二端子之间的电容。 在一些实施例中，第一终端包括RF +终端，第二终端包括RF终端。 根据一些实施例，DTC包括从最低有效位（LSB）到最高有效位（MSB）子电路有意义地排列的多个子电路，其中多个有效位子电路并联耦合在一起 并且其中每个子电路具有耦合到第一RF终端的第一节点和耦合到第二RF终端的第二节点。 DTC还包括用于接收数字控制字的输入装置，其中数字控制字包括从LSB到MSB的有意义的类似排序的比特。 数字控制字的每个有效位耦合到DTC的相应和相关联的有效位子电路，从而控制相关子电路的开关操作。 使用单位单元实现DTC，其中LSB子电路包括单个单元。 下一个有效位子电路包括用于实现其相关联和对应的先前有效位子电路的单位电池数量的x个实例，其中值x取决于用于对有效位子电路进行加权的加权编码 DTC。 DTC可以根据二进制代码，温度计代码，二者的组合或任何其他方便有用的代码进行加权。 在许多实施例中，单元电池包括与电容器串联的多个堆叠的FET。 单元电池还可以包括耦合到层叠FET的栅极的多个栅极电阻器R G以及耦合在堆叠FET的漏极和源极之间的多个R DS电阻器。 堆叠FET提高了DTC的功率处理能力，使其达到或超过了当前和未来通信标准所强加的高功率处理要求。

    Power device control circuit and power device circuit
    100.
    发明专利
    Power device control circuit and power device circuit 有权
    电源设备控制电路和电源设备电路

    公开(公告)号：JP2013168905A

    公开(公告)日：2013-08-29

    申请号：JP2012032529

    申请日：2012-02-17

    Applicant: Mitsubishi Electric Corp ,  三菱電機株式会社

    Inventor： UOTA SHIORI ,  INOUE TAKAHIRO ,  TAMAKI TSUNEJI ,  ORITA SHOICHI

    IPC: H03K17/16 ,  H02M1/08 ,  H02M1/44 ,  H03K17/04 ,  H03K17/687

    CPC classification number: G05F1/66 ,  H02M1/08 ,  H02M1/44 ,  H02M2001/0054 ,  H03K3/012 ,  H03K17/0406 ,  H03K17/162 ,  H03K17/168 ,  H03K2217/0036 ,  Y02B70/1491

    Abstract: PROBLEM TO BE SOLVED: To provide a power device control circuit that inexpensively reconciles EMI noise suppression and switching loss suppression.SOLUTION: A power device control circuit 200 for inputting a gate drive signal into a gate terminal 100a of a power device 100 includes: a control signal input circuit 2 for receiving a power device control signal 1a for controlling the power device 100; a drive system control circuit 4 connected to the control signal input circuit 2; a drive circuit 5 with a plurality of drive systems 5a, 5b, 5c for driving the power device 100 on receipt of a drive circuit control signal 1c from the drive system control circuit 4; and a timer circuit 3 for selecting the drive system 5b in response to the drive circuit control signal 1c a fixed time after the input of a predetermined signal, that is, the power device control signal 1a to change a driving capability of the drive system control circuit 4 to drive the power device 100.

    Abstract translation: 要解决的问题：提供廉价地调节EMI噪声抑制和开关损耗抑制的功率器件控制电路。解决方案：用于将栅极驱动信号输入到功率器件100的栅极端子100a的功率器件控制电路200包括： 控制信号输入电路2，用于接收用于控制功率器件100的功率器件控制信号1a; 连接到控制信号输入电路2的驱动系统控制电路4; 具有多个驱动系统5a，5b，5c的驱动电路5，用于在从驱动系统控制电路4接收到驱动电路控制信号1c时驱动电力设备100; 以及定时器电路3，用于在输入预定信号之后的固定时间（即，功率器件控制信号1a）响应于驱动电路控制信号1c选择驱动系统5b，以改变驱动系统控制的驱动能力 电路4以驱动功率器件100。

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