公开(公告)号：JP2004193618A

公开(公告)日：2004-07-08

申请号：JP2003411658

申请日：2003-12-10

申请人： Glenn J Leedy ,  リーディ,グレン・ジェイ

发明人： LEEDY GLENN J

IPC分类号： G21K5/02 ,  B81B3/00 ,  G02F1/13 ,  G03F7/20 ,  G11C29/00 ,  H01L21/027 ,  H01L21/306 ,  H01L21/331 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/764 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/98 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H01L27/00 ,  H01L27/02 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/732 ,  H01L29/78 ,  H01L29/786 ,  H05G1/00

CPC分类号： H01L25/50 ,  G02F1/13452 ,  G02F2001/136281 ,  G03F7/70658 ,  G11C29/006 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0655 ,  H01L27/0207 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/938 ,  Y10S438/942 ,  Y10S438/967 ,  Y10S438/977 ,  Y10T29/49128 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49171 ,  Y10T29/4921 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/80001

摘要： PROBLEM TO BE SOLVED: To provide a lithography apparatus for semiconductor processing for generating a mask-less pattern using a MDI process technique. SOLUTION: The lithography apparatus for semiconductor processing for generating a mask-less pattern includes, a source integrated light valve (SLV) array 420 of radiation source cells (RSCs) which are formed on a flexible insulating film supported by a supporting frame 426 and arranged in a matrix; and control logic mechanisms 424 which are arranged on the film for controlling the cells, each cell including a radiation source, a target on which radiation is incident to generate x-rays, and an aperture (REA) for radiating x-rays on a surface to be exposed by the target. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2008270797A

公开(公告)日：2008-11-06

申请号：JP2008100868

申请日：2008-04-08

申请人： Glenn J Leedy ,  リーディ グレン ジェイ

发明人： LEEDY GLENN J

IPC分类号： G21K5/02 ,  H01L21/02 ,  B81B3/00 ,  G02F1/13 ,  G03F7/20 ,  G11C29/00 ,  H01L21/027 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/331 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/764 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/98 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L27/00 ,  H01L27/02 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/73 ,  H01L29/732 ,  H01L29/737 ,  H01L29/78 ,  H01L29/786 ,  H01L29/84 ,  H05G1/00

CPC分类号： H01L25/50 ,  G02F1/13452 ,  G02F2001/136281 ,  G03F7/70658 ,  G11C29/006 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0655 ,  H01L27/0207 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/938 ,  Y10S438/942 ,  Y10S438/967 ,  Y10S438/977 ,  Y10T29/49128 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49171 ,  Y10T29/4921 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/80001

摘要： PROBLEM TO BE SOLVED: To provide a general-purpose method for manufacturing integrated circuits (24, 26, 28, to 30) by using a flexible film formed by an ultra-thin stress-reducing dielectric material such as a silicon dioxide and a silicon nitride and a semiconductor layer. SOLUTION: Semiconductor devices (24, 26, 28 to 30) are formed in a semiconductor layer of a film (36). First, a semiconductor film layer (36) is formed of a substrate (18) of a standard thickness, and next, a thin surface layer of the substrate is etched or polished. In other versions, a support for a conventional bonding integrated circuit die and a flexible film as electrically mutual connection are used, and mutual connection parts are formed in a plurality of layers in the film, and according to this method, a plurality of dies can be connected to one of the films, and the film is subsequently packaged as a multi-chip module. COPYRIGHT: (C)2009,JPO&INPIT

摘要翻译： 要解决的问题：为了提供通过使用由超薄应力降低电介质材料形成的柔性膜来制造集成电路（24,26,38,30）的通用方法，例如二氧化硅 以及氮化硅和半导体层。 解决方案：半导体器件（24,26,28至30）形成在膜（36）的半导体层中。 首先，半导体膜层（36）由标准厚度的基板（18）形成，接着，蚀刻或抛光基板的薄表面层。 在其他形式中，使用对传统的接合集成电路管芯和柔性膜作为电气互连的支撑件，并且相互连接部分形成在膜中的多个层中，并且根据该方法，多个管芯可以 连接到其中一个膜，并且膜随后被封装成多芯片模块。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2004179670A

公开(公告)日：2004-06-24

申请号：JP2003411689

申请日：2003-12-10

申请人： Glenn J Leedy ,  リーディ,グレン・ジェイ

发明人： LEEDY GLENN J

IPC分类号： G21K5/02 ,  B81B3/00 ,  G02F1/13 ,  G03F7/20 ,  G11C29/00 ,  H01L21/027 ,  H01L21/306 ,  H01L21/331 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/764 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/98 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H01L27/00 ,  H01L27/02 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/732 ,  H01L29/78 ,  H01L29/786 ,  H05G1/00

CPC分类号： H01L25/50 ,  G02F1/13452 ,  G02F2001/136281 ,  G03F7/70658 ,  G11C29/006 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0655 ,  H01L27/0207 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/938 ,  Y10S438/942 ,  Y10S438/967 ,  Y10S438/977 ,  Y10T29/49128 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49171 ,  Y10T29/4921 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/80001

摘要： PROBLEM TO BE SOLVED: To provide a versatile method for manufacturing an integrated circuit by a flexible film formed by an extremely thin stress reducing dielectric material such as silicon dioxide and silicon nitride and a semiconductor layer. SOLUTION: Semiconductor devices (24, 26, 28 to 30) are formed in a semiconductor layer of a film (36). At first, the semiconductor film layer (36) is formed from a substrate (18) of standard thickness, and next, a thin surface layer of the substrate is etched or polished. In other version, a support for the conventional bonding integrated circuit die and a flexible film as electrically mutual connection are used, and a mutual connection part is formed in a plurality of layers in the film. By this method, a plurality of dies can be connected to one of the films, and the film is subsequently packaged as a multi-chip module. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2008166832A

公开(公告)日：2008-07-17

申请号：JP2008013189

申请日：2008-01-23

申请人： Glenn J Leedy ,  グレン ジェイ リーディ

发明人： LEEDY GLENN J

IPC分类号： G11C11/401 ,  H01L25/065 ,  G11C5/02 ,  G11C5/04 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8244 ,  H01L21/8246 ,  H01L21/8247 ,  H01L25/07 ,  H01L25/18 ,  H01L27/06 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L43/08

CPC分类号： H01L27/10897 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C29/44 ,  G11C29/81 ,  G11C29/846 ,  G11C29/848 ,  H01L23/481 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/8083 ,  H01L2225/06541 ,  H01L2924/01079 ,  Y10S438/977 ,  H01L2924/00014

摘要： PROBLEM TO BE SOLVED: To reduce manufacturing costs per unit megabyte in a memory to less than half and more than one tenth the manufacturing costs of a circuit commonly manufactured by a monolithic circuit integration method simply.
SOLUTION: In a three-dimensional (3DS) memory 100, a memory circuit 103 and a control logic circuit 101 can be physically separated onto each layer 103 to optimize each layer separately. For several memory circuits 103, one control logic circuit 101 is sufficient, thus reducing the costs. The manufacture of the 3DS memory 100 has a step of thinning the thickness of the memory circuit 103 to not more than 50 μm, and a step of joining the memory circuit to a circuit laminate in a wafer substrate form. A high-density interlayer vertical bus interconnection section 105 of particulates is used. A method of manufacturing the 3DS memory 100 enables some performance and physical size efficiency and is executed by an established semiconductor machining technique.
COPYRIGHT: (C)2008,JPO&INPIT

摘要翻译： 要解决的问题：为了将存储器中的每单位兆字节的制造成本降低到简单地通过单片电路集成方法通常制造的电路的制造成本的不到一半和十分之一以上。 解决方案：在三维（3DS）存储器100中，存储器电路103和控制逻辑电路101可以物理地分离到每个层103上以分别优化每个层。 对于多个存储器电路103，一个控制逻辑电路101是足够的，因此降低了成本。 3DS存储器100的制造具有将存储电路103的厚度减薄到不大于50μm的步骤，以及将存储电路连接到晶片衬底形式的电路层叠体的步骤。 使用微粒的高密度层间垂直总线互连部105。 制造3DS存储器100的方法能够实现一些性能和物理尺寸效率，并且通过已建立的半导体加工技术执行。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008172254A

公开(公告)日：2008-07-24

申请号：JP2008013190

申请日：2008-01-23

申请人： Glenn J Leedy ,  グレン ジェイ リーディ

发明人： LEEDY GLENN J

IPC分类号： G11C11/401 ,  H01L25/065 ,  G11C5/02 ,  G11C5/04 ,  H01L21/768 ,  H01L21/8242 ,  H01L25/07 ,  H01L25/18 ,  H01L27/00 ,  H01L27/06 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/10897 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C29/44 ,  G11C29/81 ,  G11C29/846 ,  G11C29/848 ,  H01L23/481 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/8083 ,  H01L2225/06541 ,  H01L2924/01079 ,  Y10S438/977 ,  H01L2924/00014

摘要： PROBLEM TO BE SOLVED: To reduce the manufacturing cost per megabyte of a memory for a fraction of the cost for conventionally manufacturing, merely by a monolithic circuit integration method. SOLUTION: A three-dimensional structure (3DS) memory (100) allows for the physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers, such that each layer is separately optimized. One control logic circuit (101) is sufficient for several memory circuits (103), and cost can be reduced. Fabrication of 3DS memory (100) includes a step of thinning of the memory circuit (103) to smaller than 50 μm in thickness, and a step of bonding the memory circuit to a circuit stack, while still in wafer substrate form. Fine-grain high density interlayer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies and is implemented with established semiconductor processing techniques. COPYRIGHT: (C)2008,JPO&INPIT

摘要翻译： 要解决的问题：仅通过单片电路集成方法来降低传统制造成本的一小部分的每兆字节存储器的制造成本。 解决方案：三维结构（3DS）存储器（100）允许将存储器电路（103）和控制逻辑电路（101）物理分离到不同的层上，使得每个层被分别优化。 一个控制逻辑电路（101）对于多个存储器电路（103）是足够的，并且可以降低成本。 3DS存储器（100）的制造包括将存储器电路（103）的薄型化至小于50μm的步骤，以及将晶体衬底形式的存储电路结合到电路堆叠的步骤。 使用细粒高密度层间垂直总线连接（105）。 3DS存储器（100）制造方法能够实现几种性能和物理尺寸效率，并且通过已建立的半导体处理技术来实现。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008166831A

公开(公告)日：2008-07-17

申请号：JP2008013188

申请日：2008-01-23

申请人： Glenn J Leedy ,  グレン ジェイ リーディ

发明人： LEEDY GLENN J

IPC分类号： G11C11/401 ,  H01L25/065 ,  G11C5/02 ,  G11C5/04 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8244 ,  H01L21/8246 ,  H01L21/8247 ,  H01L25/07 ,  H01L25/18 ,  H01L27/06 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L43/08

CPC分类号： H01L27/10897 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C29/44 ,  G11C29/81 ,  G11C29/846 ,  G11C29/848 ,  H01L23/481 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/8083 ,  H01L2225/06541 ,  H01L2924/01079 ,  Y10S438/977 ,  H01L2924/00014

摘要： PROBLEM TO BE SOLVED: To reduce manufacturing costs per unit megabyte in a memory to less than half and more than one tenth the manufacturing costs of a circuit commonly manufactured by a monolithic circuit integration method simply.
SOLUTION: In a three-dimensional (3DS) memory 100, a memory circuit 103 and a control logic circuit 101 can be physically separated onto each layer 103 to optimize each layer separately. For several memory circuits 103, one control logic circuit 101 is sufficient, thus reducing the costs. The manufacture of the 3DS memory 100 has a step of thinning the thickness of the memory circuit 103 to not more than 50 μm, and a step of joining the memory circuit to a circuit laminate in a wafer substrate form. A high-density interlayer vertical bus interconnection section 105 of particulates is used. A method of manufacturing the 3DS memory 100 enables some performance and physical size efficiency and is executed by an established semiconductor machining technique.
COPYRIGHT: (C)2008,JPO&INPIT

摘要翻译： 要解决的问题：为了将存储器中的每单位兆字节的制造成本降低到简单地通过单片电路集成方法通常制造的电路的制造成本的不到一半和十分之一以上。 解决方案：在三维（3DS）存储器100中，存储器电路103和控制逻辑电路101可以物理地分离到每个层103上以分别优化每个层。 对于多个存储器电路103，一个控制逻辑电路101是足够的，因此降低了成本。 3DS存储器100的制造具有将存储电路103的厚度减薄到不大于50μm的步骤，以及将存储电路连接到晶片衬底形式的电路层叠体的步骤。 使用微粒的高密度层间垂直总线互连部105。 制造3DS存储器100的方法能够实现一些性能和物理尺寸效率，并且通过已建立的半导体加工技术执行。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2011181176A

公开(公告)日：2011-09-15

申请号：JP2011119212

申请日：2011-05-27

申请人： Glenn J Leedy ,  グレン ジェイ リーディ

发明人： LEEDY GLENN J

IPC分类号： G11C11/401 ,  G11C5/02 ,  G11C5/04 ,  H01L21/768 ,  H01L21/8246 ,  H01L25/04 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/06 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/10897 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C29/44 ,  G11C29/81 ,  G11C29/846 ,  G11C29/848 ,  H01L23/481 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/8083 ,  H01L2225/06541 ,  H01L2924/01079 ,  Y10S438/977 ,  H01L2924/00014

摘要： PROBLEM TO BE SOLVED: To reduce a memory manufacturing cost per unit mega byte to a fraction of a the cost of conventional circuit which is monolithically manufactured merely by a circuit integration method. SOLUTION: In a three-dimensional (3DS) memory (100) enabling the physical separation of memory circuits (103) and control logic circuits (101) mounted to separate layers (103) so as to independently optimize each layer, a single control logic circuit (101) is sufficed for a few number of memory circuits (103), and thus, the cost can be reduced. To manufacture the 3DS memory (100), a process of thinning each memory circuit (103) to the thickness of 50 μm or less, and a process of joining the memory circuit to a circuit lamination body in a wafer substrate form intact are provided. A fine-particle high-density interlayer vertical bus interconnection unit (105) is used. The manufacturing method of the 3DS memory (100) is carried out by an established semiconductor process technology which is enabled and established in several categories of performance and physical size efficiency. COPYRIGHT: (C)2011,JPO&INPIT

摘要翻译： 要解决的问题：为了将每单位兆字节的存储器制造成本降低到仅通过电路集成方法单片制造的传统电路的成本的一小部分。 解决方案：在三维（3DS）存储器（100）中，使得存储电路（103）和安装到分离层（103）的控制逻辑电路（101）的物理分离能够独立地优化每个层， 单个控制逻辑电路（101）可用于少量存储器电路（103），从而可以降低成本。 为了制造3DS存储器（100），提供了将每个存储器电路（103）减薄到50μm以下的厚度的处理，以及将存储电路连接到晶片衬底中的电路层叠体的处理完整的过程。 使用细粒子高密度层间垂直总线互连单元（105）。 3DS存储器（100）的制造方法通过已建立的半导体工艺技术进行，该技术在几类性能和物理尺寸效率下被实现和建立。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2008028407A

公开(公告)日：2008-02-07

申请号：JP2007211038

申请日：2007-08-13

申请人： Glenn J Leedy ,  グレン ジェイ リーディ

发明人： LEEDY GLENN J

IPC分类号： G11C11/401 ,  H01L27/00 ,  G11C5/02 ,  G11C5/04 ,  G11C29/12 ,  H01L21/768 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/06 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/10897 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C29/44 ,  G11C29/81 ,  G11C29/846 ,  G11C29/848 ,  H01L23/481 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/8083 ,  H01L2225/06541 ,  H01L2924/01079 ,  Y10S438/977 ,  H01L2924/00014

摘要： PROBLEM TO BE SOLVED: To reduce fabrication cost per megabyte of a memory to a fraction of that of a circuit just conventionally fabricated with a monolithic circuit integration method.
SOLUTION: A three-dimensional structure (3DS) memory 100 allows physical separation of the memory circuits 103 and the control logic circuit 101 onto different layers 103 such that each layer may be separately optimized. One control logic circuit 101 suffices for several memory circuits 103, reducing cost. Fabrication of 3DS memory 100 involves thinning of the memory circuit 103 to less than 50 μm in thickness and bonding the circuit to a circuit stack while keeping still in wafer substrate form. Fine-grain high density interlayer vertical bus connections 105 are used. The 3DS memory 100 manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
COPYRIGHT: (C)2008,JPO&INPIT

摘要翻译： 要解决的问题：将每兆字节存储器的制造成本降低到刚刚通过单片电路集成方法制造的电路的制造成本的一小部分。 解决方案：三维结构（3DS）存储器100允许将存储器电路103和控制逻辑电路101物理分离到不同的层103上，使得每个层可以被单独优化。 一个控制逻辑电路101足以用于多个存储器电路103，从而降低成本。 3DS存储器100的制造涉及将存储器电路103的薄型化到小于50μm的厚度，并且将电路结合到电路堆叠，同时保持晶片衬底形式。 使用细粒高密度层间垂直总线连接105。 3DS存储器100制造方法实现了几种性能和物理尺寸效率，并且通过已建立的半导体处理技术来实现。 版权所有（C）2008，JPO＆INPIT