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12 条记录 (耗时 0.018 秒)

    Phased NAND power-on reset
    1.
    发明授权
    Phased NAND power-on reset 有权
    分阶段NAND上电复位

    公开(公告)号：US08924626B2

    公开(公告)日：2014-12-30

    申请号：US12770358

    申请日：2010-04-29

    申请人： Steven S. Cheng ,  Dennis Ea ,  Jianmin Huang ,  Alexander Kwok-Tung Mak ,  Farookh Moogat

    发明人： Steven S. Cheng ,  Dennis Ea ,  Jianmin Huang ,  Alexander Kwok-Tung Mak ,  Farookh Moogat

    IPC分类号： G06F12/00 ,  G06F1/24

    CPC分类号： G06F1/24

    摘要： A method and system for phasing power-intensive operations is disclosed. A non-volatile storage device controller detects a power reset. The controller is in communication with non-volatile memories in the non-volatile storage device. In response to detecting a power reset, the controller determines a current consumption necessary to reset the non-volatile memories in the non-volatile storage device. The controller simultaneously resets all of the non-volatile memories when the determined current consumption is less than a current consumption threshold. If the determined current consumption is greater than the current consumption threshold, the controller resets a first subset of the plurality of non-volatile memories, and after a predetermined delay, resets a second subset of the non-volatile memories. Therefore, a power-intensive operation may be performed without exceeding a current consumption threshold by dividing the operation into a sequence of steps that do not exceed the threshold.

    摘要翻译： 公开了一种用于阶段性强力密集型操作的方法和系统。 非易失性存储设备控制器检测电源复位。 控制器与非易失性存储设备中的非易失性存储器通信。 响应于检测到电源复位，控制器确定复位非易失性存储设备中的非易失性存储器所需的电流消耗。 当确定的电流消耗小于电流消耗阈值时，控制器同时复位所有非易失性存储器。 如果确定的电流消耗大于当前消耗阈值，则控制器复位多个非易失性存储器的第一子集，并且在预定延迟之后，复位非易失性存储器的第二子集。 因此，通过将操作划分成不超过阈值的一系列步骤，可以不超过电流消耗阈值来执行功率密集型操作。

    Structure and method for shuffling data within non-volatile memory devices
    3.
    发明授权
    Structure and method for shuffling data within non-volatile memory devices 有权
    在非易失性存储器件内混洗数据的结构和方法

    公开(公告)号：US08228729B2

    公开(公告)日：2012-07-24

    申请号：US13333494

    申请日：2011-12-21

    申请人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-Ho Kim

    发明人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-Ho Kim

    IPC分类号： G11C16/04 ,  G11C7/10

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/34 ,  G11C2211/5641 ,  G11C2211/5642

    摘要： Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

    摘要翻译： 描述用于在多状态非易失性存储器中读取和写入数据的技术。 数据以二进制格式写入存储器，读入存储器中的数据寄存器，并在寄存器内“折叠”，然后以多状态格式写入存储器。 在折叠操作中，来自单个字线的二进制数据被折叠为多状态格式，并且当以多状态形式重写时，被写入另一个字线的仅一部分。 还描述了数据“展开”的相应的读取技术。 还提出了允许这种“折叠”操作的寄存器结构。 一组实施例包括本地内部数据总线，其允许在不同读/写堆栈的寄存器之间的数据，其中内部总线可以在内部数据折叠处理中使用。

    Structure and Method for Shuffling Data Within Non-Volatile Memory Devices
    4.
    发明申请
    Structure and Method for Shuffling Data Within Non-Volatile Memory Devices 有权
    在非易失性存储器件中进行数据混合的结构和方法

    公开(公告)号：US20120113716A1

    公开(公告)日：2012-05-10

    申请号：US13333494

    申请日：2011-12-21

    申请人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-ho Kim

    发明人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-ho Kim

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/34 ,  G11C2211/5641 ,  G11C2211/5642

    摘要： Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

    摘要翻译： 描述用于在多状态非易失性存储器中读取和写入数据的技术。 数据以二进制格式写入存储器，读入存储器中的数据寄存器，并在寄存器内“折叠”，然后以多状态格式写入存储器。 在折叠操作中，来自单个字线的二进制数据被折叠为多状态格式，并且当以多状态形式重写时，被写入另一个字线的仅一部分。 还描述了数据“展开”的相应的读取技术。 还提出了允许这种“折叠”操作的寄存器结构。 一组实施例包括本地内部数据总线，其允许在不同读/写堆栈的寄存器之间的数据，其中内部总线可以在内部数据折叠处理中使用。

    Structure and method for shuffling data within non-volatile memory devices
    7.
    发明授权
    Structure and method for shuffling data within non-volatile memory devices 有权
    在非易失性存储器件内混洗数据的结构和方法

    公开(公告)号：US08102705B2

    公开(公告)日：2012-01-24

    申请号：US12635449

    申请日：2009-12-10

    申请人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-ho Kim

    发明人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-ho Kim

    IPC分类号： G11C16/04 ,  G11C7/10

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/34 ,  G11C2211/5641 ,  G11C2211/5642

    摘要： Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

    摘要翻译： 描述用于在多状态非易失性存储器中读取和写入数据的技术。 数据以二进制格式写入存储器，读入存储器中的数据寄存器，并在寄存器内“折叠”，然后以多状态格式写入存储器。 在折叠操作中，来自单个字线的二进制数据被折叠为多状态格式，并且当以多状态形式重写时，被写入另一个字线的仅一部分。 还描述了数据“展开”的相应的读取技术。 这些技术还允许在控制器上用纠错码（ECC）对数据进行编码，该错误校正码在将数据传送到存储器以二进制形式写入之前考虑其最终的多状态存储。 还提出了允许这种“折叠”操作的寄存器结构。 一组实施例包括本地内部数据总线，其允许在不同读/写堆栈的寄存器之间的数据，其中内部总线可以在内部数据折叠处理中使用。

    PHASED NAND POWER-ON RESET
    8.
    发明申请
    PHASED NAND POWER-ON RESET 有权
    复位NAND上电复位

    公开(公告)号：US20110271036A1

    公开(公告)日：2011-11-03

    申请号：US12770358

    申请日：2010-04-29

    申请人： Steven S. Cheng ,  Dennis Ea ,  Jianmin Huang ,  Alexander Kwok-Tung Mak ,  Farookh Moogat

    发明人： Steven S. Cheng ,  Dennis Ea ,  Jianmin Huang ,  Alexander Kwok-Tung Mak ,  Farookh Moogat

    IPC分类号： G06F12/00 ,  G06F1/26 ,  G06F12/02

    CPC分类号： G06F1/24

    摘要： A method and system for phasing power-intensive operations is disclosed. A non-volatile storage device controller detects a power reset. The controller is in communication with non-volatile memories in the non-volatile storage device. In response to detecting a power reset, the controller determines a current consumption necessary to reset the non-volatile memories in the non-volatile storage device. The controller simultaneously resets all of the non-volatile memories when the determined current consumption is less than a current consumption threshold. If the determined current consumption is greater than the current consumption threshold, the controller resets a first subset of the plurality of non-volatile memories, and after a predetermined delay, resets a second subset of the non-volatile memories. Therefore, a power-intensive operation may be performed without exceeding a current consumption threshold by dividing the operation into a sequence of steps that do not exceed the threshold.

    摘要翻译： 公开了一种用于阶段性强力密集型操作的方法和系统。 非易失性存储设备控制器检测电源复位。 控制器与非易失性存储设备中的非易失性存储器通信。 响应于检测到电源复位，控制器确定复位非易失性存储设备中的非易失性存储器所需的电流消耗。 当确定的电流消耗小于电流消耗阈值时，控制器同时复位所有非易失性存储器。 如果确定的电流消耗大于当前消耗阈值，则控制器复位多个非易失性存储器的第一子集，并且在预定延迟之后，复位非易失性存储器的第二子集。 因此，通过将操作划分成不超过阈值的一系列步骤，可以不超过电流消耗阈值来执行功率密集型操作。

    Non-volatile memory and method with improved data scrambling
    10.
    发明授权
    Non-volatile memory and method with improved data scrambling 有权
    非易失性存储器和具有改进的数据加扰的方法

    公开(公告)号：US08843693B2

    公开(公告)日：2014-09-23

    申请号：US13109972

    申请日：2011-05-17

    申请人： Jonathan Hsu ,  Chris Nga Yee Avila ,  Alexander Kwok-Tung Mak ,  Sergey Anatolievich Gorobets ,  Tien-chien Kuo ,  Yee Lih Koh ,  Jun Wan

    发明人： Jonathan Hsu ,  Chris Nga Yee Avila ,  Alexander Kwok-Tung Mak ,  Sergey Anatolievich Gorobets ,  Tien-chien Kuo ,  Yee Lih Koh ,  Jun Wan

    IPC分类号： G06F12/00 ,  G11C7/10 ,  G11C16/34 ,  G06F12/14

    CPC分类号： G11C16/3427 ,  G06F12/1408 ,  G11C7/1006 ,  G11C7/1012

    摘要： A memory device cooperating with a memory controller scrambles each unit of data using a selected scrambling key before storing it in an array of nonvolatile memory cells. This helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. For a given page of data having a logical address and for storing at a physical address, the key is selected from a finite sequence thereof as a function of both the logical address and the physical address. In a block management scheme the memory array is organized into erase blocks, the physical address is the relative page number in each block. When logical address are grouped into logical groups and manipulated as a group and each group is storable into a sub-block, the physical address is the relative page number in the sub-block.

    摘要翻译： 与存储器控制器协作的存储器件在将其存储在非易失性存储器单元阵列之前，使用所选择的加密密钥对每个数据单元进行加扰。 这有助于减少由特定数据模式的重复和长期存储引起的编程干扰，用户读取干扰和浮动栅极到浮动栅极耦合。 对于具有逻辑地址并用于存储在物理地址的给定页面的数据，从作为逻辑地址和物理地址的函数的有限序列中选择密钥。 在块管理方案中，存储器阵列被组织成擦除块，物理地址是每个块中的相对页号。 当逻辑地址分组为逻辑组并作为组操作并且每个组可存储到子块中时，物理地址是子块中的相对页号。