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公开(公告)号：US07876630B1
公开(公告)日：2011-01-25
申请号：US11935405
申请日：2007-11-06
申请人： Philip Clarke , Andrew Bellis , Yan Chong , Joseph Huang , Michael H. M. Chu
发明人： Philip Clarke , Andrew Bellis , Yan Chong , Joseph Huang , Michael H. M. Chu
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222
摘要： Circuits, methods, and apparatus that isolate an input register from spurious transitions on a DQS signal. One example receives an enable signal from a core. A logic circuit, which may be referred to as a one-half period circuit, shortens enable pulses at their front end by one-half a period. The shortened enable signal is passed to a storage element such as a register. Active pulses of the shortened enable signal clear the register, which provides a control signal closing a switch, such as an AND gate. The switch passes the DQS signal to the input register when closed and isolates the input register from the DQS signal when open. The shortened enable signal prevents the switch from opening early and passing spurious transitions on the DQS signal, for example during back-to-back non-consecutive read cycles.
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公开(公告)号：US07990786B2
公开(公告)日：2011-08-02
申请号：US12539582
申请日：2009-08-11
申请人： Michael H. M. Chu , Joseph Huang , Chiakang Sung , Yan Chong , Andrew Bellis , Philip Clarke , Manoj B. Roge
发明人： Michael H. M. Chu , Joseph Huang , Chiakang Sung , Yan Chong , Andrew Bellis , Philip Clarke , Manoj B. Roge
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , H03L7/06 , H03L7/0812
摘要： Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.
摘要翻译： 用于将数据从设备的输入时钟域传送到核心时钟域的电路，方法和装置。 一个例子是通过在输入和电路之间使用重新定时元件实现这一点。 重新定时元素通过逐渐扫描延迟并在每个增量处接收数据进行校准。 平均接收无差错数据的最小和最大延迟。 然后可以使用该平均值来调整插入由输入选通信号计时的输入寄存器和由核心时钟信号计时的输出寄存器之间的输入路径中的电路元件的定时。 在一个示例中，输入信号可以被延迟与延迟设置相对应的量。 在其他示例中，使用输入寄存器和输出寄存器之间的中间寄存器来注册每个输入信号，其中时钟信号被延迟与延迟设置相对应的量。
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公开(公告)号：US07983094B1
公开(公告)日：2011-07-19
申请号：US12539594
申请日：2009-08-11
申请人： Manoj B. Roge , Andrew Bellis , Philip Clarke , Joseph Huang , Michael H. M. Chu , Yan Chong
发明人： Manoj B. Roge , Andrew Bellis , Philip Clarke , Joseph Huang , Michael H. M. Chu , Yan Chong
CPC分类号： G11C7/22 , G11C5/04 , G11C7/04 , G11C7/10 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. This includes adjusting read and write DQS signal timing for each DQ/DQS group, as well as inserting or bypassing registers when timing errors are more than one clock cycle. Timing skew caused by trace and driver mismatches between CK, DQ, and DQS signals are compensated for. One or more of these calibrations may be updated by a tracking routine during device operation.
摘要翻译： 提供高速存储器接口的输入和输出电路校准的电路，方法和设备。 由存储器接口提供的时钟信号的飞越路由引起的定时错误针对读取和写入路径进行校准。 这包括调整每个DQ / DQS组的读和写DQS信号定时，以及当定时误差大于一个时钟周期时插入或旁路寄存器。 由CK，DQ和DQS信号之间的跟踪和驱动器不匹配引起的定时偏移被补偿。 这些校准中的一个或多个可以在设备操作期间通过跟踪例程更新。
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公开(公告)号：US20090296503A1
公开(公告)日：2009-12-03
申请号：US12539582
申请日：2009-08-11
申请人： Michael H.M. Chu , Joseph Huang , Chiakang Sung , Yan Chong , Andrew Bellis , Philip Clarke , Manoj B. Roge
发明人： Michael H.M. Chu , Joseph Huang , Chiakang Sung , Yan Chong , Andrew Bellis , Philip Clarke , Manoj B. Roge
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , H03L7/06 , H03L7/0812
摘要： Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.
摘要翻译： 用于将数据从设备的输入时钟域传送到核心时钟域的电路，方法和装置。 一个例子是通过在输入和电路之间使用重新定时元件实现这一点。 重新定时元素通过逐渐扫描延迟并在每个增量处接收数据进行校准。 平均接收无差错数据的最小和最大延迟。 然后可以使用该平均值来调整插入由输入选通信号计时的输入寄存器和由核心时钟信号计时的输出寄存器之间的输入路径中的电路元件的定时。 在一个示例中，输入信号可以被延迟与延迟设置相对应的量。 在其他示例中，使用输入寄存器和输出寄存器之间的中间寄存器来注册每个输入信号，其中时钟信号被延迟与延迟设置相对应的量。
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公开(公告)号：US07590008B1
公开(公告)日：2009-09-15
申请号：US11936036
申请日：2007-11-06
申请人： Manoj B. Roge , Andrew Bellis , Philip Clarke , Joseph Huang , Michael H. M. Chu , Yan Chong
发明人： Manoj B. Roge , Andrew Bellis , Philip Clarke , Joseph Huang , Michael H. M. Chu , Yan Chong
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C5/04 , G11C7/04 , G11C7/10 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. This includes adjusting read and write DQS signal timing for each DQ/DQS group, as well as inserting or bypassing registers when timing errors are more than one clock cycle. Timing skew caused by trace and driver mismatches between CK, DQ, and DQS signals are compensated for. One or more of these calibrations may be updated by a tracking routine during device operation.
摘要翻译： 提供高速存储器接口的输入和输出电路校准的电路，方法和设备。 由存储器接口提供的时钟信号的飞越路由引起的定时错误针对读取和写入路径进行校准。 这包括调整每个DQ / DQS组的读和写DQS信号定时，以及当定时误差大于一个时钟周期时插入或旁路寄存器。 由CK，DQ和DQS信号之间的跟踪和驱动器不匹配引起的定时偏移被补偿。 这些校准中的一个或多个可以在设备操作期间通过跟踪例程更新。
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公开(公告)号：US09515880B1
公开(公告)日：2016-12-06
申请号：US13338898
申请日：2011-12-28
CPC分类号： H04L41/0816 , G06F1/04 , G06F1/10 , G06F9/44505 , G06F17/5054 , H04J3/0688 , H04J3/0691 , H04J3/0697 , H04L41/0813
摘要： An integrated circuit device may include processing circuits that can be dynamically reconfigured to perform different tasks each of which utilizes different system clock resources. The device may include clock selection circuitry that can selectively route desired clock signals to corresponding processing circuits. The clock signal provided to each processing circuit may be selected based on a current configuration of that processing circuit. Client processing circuits in a network switch may be coupled to interchangeable client networks. The client processing circuits may be dynamically reconfigured based on characteristics of the client networks that are currently coupled to the network switch. By dynamically selecting which clock resources are provided to the processing circuits, clock resources such as global clock signals that are relatively scarce may be reserved for processing circuits that can only function with the relatively scarce clock resources. Arranged in this way, clock resource utilization may be continuously optimized.
摘要翻译： 集成电路设备可以包括可以动态地重新配置以执行不同的任务的处理电路，每个任务利用不同的系统时钟资源。 该装置可以包括时钟选择电路，其可以选择性地将期望的时钟信号路由到相应的处理电路。 可以基于该处理电路的当前配置来选择提供给每个处理电路的时钟信号。 网络交换机中的客户端处理电路可以耦合到可互换的客户端网络。 可以基于当前耦合到网络交换机的客户端网络的特性来动态地重新配置客户端处理电路。 通过动态地选择哪些时钟资源被提供给处理电路，诸如相对稀少的全局时钟信号的时钟资源可以被保留用于只能用相对稀少的时钟资源起作用的处理电路。 以这种方式安排，可以不断优化时钟资源利用。
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公开(公告)号：US07990783B1
公开(公告)日：2011-08-02
申请号：US13004136
申请日：2011-01-11
申请人： Philip Clarke , Andrew Bellis , Yan Chong , Joseph Huang , Michael H. M. Chu
发明人： Philip Clarke , Andrew Bellis , Yan Chong , Joseph Huang , Michael H. M. Chu
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222
摘要： Circuits, methods, and apparatus that isolate an input register from spurious transitions on a DQS signal. One example receives an enable signal from a core. A logic circuit, which may be referred to as a one-half period circuit, shortens enable pulses at their front end by one-half a period. The shortened enable signal is passed to a storage element such as a register. Active pulses of the shortened enable signal clear the register, which provides a control signal closing a switch, such as an AND gate. The switch passes the DQS signal to the input register when closed and isolates the input register from the DQS signal when open. The shortened enable signal prevents the switch from opening early and passing spurious transitions on the DQS signal, for example during back-to-back non-consecutive read cycles.
摘要翻译： 将输入寄存器与DQS信号上的虚假转换隔离的电路，方法和设备。 一个示例从核心接收使能信号。 可以称为半周期电路的逻辑电路将其前端的使能脉冲缩短半个周期。 缩短的使能信号被传递到诸如寄存器的存储元件。 缩短的使能信号的有效脉冲清除寄存器，其提供闭合开关的控制信号，例如与门。 当开关闭合时，开关将DQS信号传送到输入寄存器，并在断开时将输入寄存器与DQS信号隔离。 缩短的使能信号防止开关在DQS信号的早期打开和传递寄生跳变，例如在背对背非连续读取周期期间。
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公开(公告)号：US07928770B1
公开(公告)日：2011-04-19
申请号：US11935347
申请日：2007-11-05
申请人： Andrew Bellis , Philip Clarke , Joseph Huang , Yan Chong , Michael H. M. Chu , Manoj B. Roge
发明人： Andrew Bellis , Philip Clarke , Joseph Huang , Yan Chong , Michael H. M. Chu , Manoj B. Roge
IPC分类号： H03K19/096
CPC分类号： G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C8/18
摘要： I/O blocks include input, output, and output enable circuits for interfacing with memory devices. The input circuit includes registers for capturing a double data rate signal, converting it into single data rate signals, and resynchronizing the single data rate signals. Multiple devices may be accessible with each device potentially having a different clock signal for resynchronizing. Another clock signal may be used to align/synchronize resulting signals from multiple devices. The resynchronized single rate signals can be converted into half-rate data signals, and the four half-rate data signals can be provided to resources in the programmable device core. The input circuit also may provide a half-rate clock signal synchronized with the half-rate data signals to the programmable device core. The half rate clock signal can be derived from the full-rate clock signal using a data strobe signal, a full-rate clock signal, or a half-rate clock signal as an input.
摘要翻译： I / O块包括用于与存储器件连接的输入，输出和输出使能电路。 输入电路包括用于捕获双倍数据速率信号的寄存器，将其转换为单个数据速率信号，并重新同步单个数据速率信号。 多个设备可以被访问，每个设备潜在地具有用于重新同步的不同的时钟信号。 另一个时钟信号可用于对准/同步来自多个设备的结果信号。 再同步的单速率信号可以转换成半速率数据信号，并且可以将四个半速率数据信号提供给可编程器件核心中的资源。 输入电路还可以将半速率数据信号同步的半速率时钟信号提供给可编程器件核心。 半速率时钟信号可以使用数据选通信号，全速率时钟信号或半速率时钟信号作为输入从全速率时钟信号导出。
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公开(公告)号：US20080291758A1
公开(公告)日：2008-11-27
申请号：US11935310
申请日：2007-11-05
申请人： Michael H.M. Chu , Joseph Huang , Chiakang Sung , Yan Chong , Andrew Bellis , Philip Clarke , Manoj B. Roge
发明人： Michael H.M. Chu , Joseph Huang , Chiakang Sung , Yan Chong , Andrew Bellis , Philip Clarke , Manoj B. Roge
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , H03L7/06 , H03L7/0812
摘要： Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.
摘要翻译： 用于将数据从设备的输入时钟域传送到核心时钟域的电路，方法和装置。 一个例子是通过在输入和电路之间使用重新定时元件实现这一点。 重新定时元素通过逐渐扫描延迟并在每个增量处接收数据进行校准。 平均接收无差错数据的最小和最大延迟。 然后可以使用该平均值来调整插入由输入选通信号计时的输入寄存器和由核心时钟信号计时的输出寄存器之间的输入路径中的电路元件的定时。 在一个示例中，输入信号可以被延迟与延迟设置相对应的量。 在其他示例中，使用输入寄存器和输出寄存器之间的中间寄存器来注册每个输入信号，其中时钟信号被延迟与延迟设置相对应的量。
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公开(公告)号：US07593273B2
公开(公告)日：2009-09-22
申请号：US11935310
申请日：2007-11-05
申请人： Michael H. M. Chu , Joseph Huang , Chiakang Sung , Yan Chong , Andrew Bellis , Philip Clarke , Manoj B. Roge
发明人： Michael H. M. Chu , Joseph Huang , Chiakang Sung , Yan Chong , Andrew Bellis , Philip Clarke , Manoj B. Roge
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , H03L7/06 , H03L7/0812
摘要： Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.
摘要翻译： 用于将数据从设备的输入时钟域传送到核心时钟域的电路，方法和装置。 一个例子是通过在输入和电路之间使用重新定时元件实现这一点。 重新定时元素通过逐渐扫描延迟并在每个增量处接收数据进行校准。 平均接收无差错数据的最小和最大延迟。 然后可以使用该平均值来调整插入由输入选通信号计时的输入寄存器和由核心时钟信号计时的输出寄存器之间的输入路径中的电路元件的定时。 在一个示例中，输入信号可以被延迟与延迟设置相对应的量。 在其他示例中，使用输入寄存器和输出寄存器之间的中间寄存器来注册每个输入信号，其中时钟信号被延迟与延迟设置相对应的量。
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