公开(公告)号：US4541078A

公开(公告)日：1985-09-10

申请号：US452155

申请日：1982-12-22

申请人： Austin C. Dumbri ,  Frank J. Procyk

发明人： Austin C. Dumbri ,  Frank J. Procyk

IPC分类号： G11C8/00 ,  G11C8/10 ,  G11C11/40

CPC分类号： G11C8/00 ,  G11C8/10

摘要： A memory of rows and columns of memory cells uses a multiplexed input address buffer having output row-column address lines which are coupled to a multiplexer and to column decoders. The multiplexer is coupled to row address decoders and serves to selectively couple the address lines to the row decoders. The address lines typically first carry row address information and then column address information. The use of a common portion of the address lines to couple the address buffer to the column decoders and multiplexer tends to reduce the overall size of the memory and thereby increases yield and reduces cost.

摘要翻译： 存储器单元的行和列的存储器使用具有耦合到多路复用器和列解码器的输出行列地址线的多路复用输入地址缓冲器。 多路复用器耦合到行地址解码器，并用于选择性地将地址线耦合到行解码器。 地址线通常首先携带行地址信息，然后传送列地址信息。 使用地址线的公共部分将地址缓冲器耦合到列解码器和多路复用器倾向于减小存储器的总体大小，从而增加产量并降低成本。

公开(公告)号：US06456101B2

公开(公告)日：2002-09-24

申请号：US09287862

申请日：1999-04-07

申请人： Austin C. Dumbri

发明人： Austin C. Dumbri

IPC分类号： G01R3102

CPC分类号： G11C29/12 ,  G01R31/3187 ,  G11C2029/1206 ,  H01L2224/16145

摘要： An auxiliary BIST circuit is constructed in a primary chip to which a secondary chip is attached, thereby allowing testing of the secondary chip using the auxiliary BIST circuit. This allows direct test access to the secondary chip without the need for a separate BIST circuit to be included in the secondary IC chip and without using a primary BIST circuit of the primary IC chip to test the secondary chip.

摘要翻译： 辅助BIST电路被构造在附接有次级芯片的主芯片中，从而允许使用辅助BIST电路测试次级芯片。 这允许对二次芯片的直接测试访问，而不需要将单独的BIST电路包括在次级IC芯片中，并且不使用主IC芯片的主BIST电路来测试次级芯片。

公开(公告)号：USRE33266E

公开(公告)日：1990-07-17

申请号：US4393

申请日：1987-01-15

申请人： Austin C. Dumbri

发明人： Austin C. Dumbri

IPC分类号： G11C29/00

CPC分类号： G11C29/787 ,  G11C29/838

摘要： A folded bit line configured DRAM, with standard even and odd rows of memory cells, also includes spare even and odd rows of memory cells which can be substituted for standard rows found to have defective cells or interconnections. Each of the decoders associated with a standard row includes provision for being disconnected if found to be associated with a defective row. One common spare decoder is associated with one spare even and one spare odd row of memory cells. Each spare decoder is designed normally to be deselected for any address but to be able to assume the address of any disconnected standard row. Disconnection of a standard decoder and substitution of a spare decoder with the appropriate even or odd row are made possible by appropriate inclusion of fusible links which are selectively opened by laser irradiation. The use of one spare decoder with both an even and odd row serves to reduce the number of needed spare decoders and thus reduces overall chip size.

公开(公告)号：US4567581A

公开(公告)日：1986-01-28

申请号：US452156

申请日：1982-12-22

申请人： Austin C. Dumbri ,  Frank J. Procyk

发明人： Austin C. Dumbri ,  Frank J. Procyk

IPC分类号： G11C8/00 ,  G11C8/10 ,  G11C11/40

CPC分类号： G11C8/10 ,  G11C8/00

摘要： A memory having multiplexed address inputs uses a column decoder which is deactivated during row address time and becomes activated during column address time. Access time and power dissipation are reduced since the column decoder need not be fully recovered after row address information has terminated and column address information is available.

摘要翻译： 具有复用地址输入的存储器使用列解码器，其在行地址时间期间被去激活，并且在列地址时间期间被激活。 降低了访问时间和功耗，因为行地址信息已经终止并且列地址信息可用后，列解码器不需要完全恢复。

公开(公告)号：US4529889A

公开(公告)日：1985-07-16

申请号：US441954

申请日：1982-11-15

申请人： Austin C. Dumbri

发明人： Austin C. Dumbri

IPC分类号： G11C7/06 ,  H03K5/02 ,  H03K19/017 ,  H03K5/13 ,  H03K5/12

CPC分类号： G11C7/06 ,  H03K19/01714 ,  H03K5/023

摘要： A sense amplifier latch voltage waveform generator circuit provides an output voltage waveform which first increases to a first potential level, which is just below the threshold voltage of a field effect transistor, and subsequently increases with an ever-increasing slope over a useful voltage range. The generated voltage waveform is applied to the gate terminal of a latch field effect transistor, which is part of a sense amplifier circuit that includes a cross-coupled pair of field effect transistors whose sources are coupled to the drain of the latch transistor and whose drain terminals receive differential memory signals. The generator circuit consists essentially of an input gating transistor, an output stage having serially connected pull-up and pull-down transistors, and another similar feedback stage which includes a bootstrap capacitor. The bootstrap capacitor is coupled to the output stage.

摘要翻译： 读出放大器锁存电压波形发生器电路提供一个输出电压波形，其首先增加到刚好低于场效应晶体管的阈值电压的第一电位电平，随后随着在有用电压范围上的不断增加的斜率而增加。 产生的电压波形被施加到锁存场效应晶体管的栅极端子，其是包括交叉耦合的一对场效应晶体管的读出放大器电路的一部分，其源极耦合到锁存晶体管的漏极并且其漏极 端子接收差分存储器信号。 发生器电路基本上由输入门控晶体管，具有串联连接的上拉和下拉晶体管的输出级以及包括自举电容器的另一类似的反馈级组成。 自举电容器耦合到输出级。

公开(公告)号：US4494220A

公开(公告)日：1985-01-15

申请号：US444239

申请日：1982-11-24

申请人： Austin C. Dumbri ,  Frank J. Procyk

发明人： Austin C. Dumbri ,  Frank J. Procyk

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C11/40

CPC分类号： G11C29/787 ,  G11C29/838

摘要： A folded bit line configured DRAM, with standard even and odd rows of memory cells, also includes spare even and odd rows of memory cells which can be substituted for standard rows found to have defective cells or interconnections. Each of the decoders associated with a standard row includes provision for being disconnected if found to be associated with a defective row. One common spare decoder is associated with one spare even and one spare odd row of memory cells. Each spare decoder is designed normally to be deselected for any address but to be able to assume the address of any disconnected standard row. Disconnection of a standard decoder and substitution of a spare decoder with the appropriate even or odd row are made possible by appropriate inclusion of fusible links which are selectively opened by laser irradiation. The use of one spare decoder with both an even and odd row serves to reduce the number of needed spare decoders and thus reduces overall chip size.

摘要翻译： 具有标准偶数行和奇数行存储器单元的折叠位线配置的DRAM还包括备用偶数和奇数行的存储器单元，其可以替代发现具有缺陷单元或互连的标准行。 与标准行相关联的每个解码器包括如果发现与缺陷行相关联的断开的设置。 一个常见的备用解码器与一个备用偶数和一个备用奇数行的存储器单元相关联。 每个备用解码器通常设计为取消任何地址的选择，但能够承担任何断开的标准行的地址。 通过适当地包括通过激光照射选择性地打开的可熔链路，使得标准解码器的断开和具有适当的偶数或奇数行的备用解码器的替代成为可能。 使用具有偶数和奇数行的一个备用解码器用于减少所需备用解码器的数量，从而减少整体芯片尺寸。

公开(公告)号：US4260909A

公开(公告)日：1981-04-07

申请号：US937951

申请日：1978-08-30

申请人： Austin C. Dumbri ,  Walter Rosenzweig

发明人： Austin C. Dumbri ,  Walter Rosenzweig

IPC分类号： G05F3/20 ,  G11C11/407 ,  G11C11/413 ,  G11C11/417 ,  H01L21/822 ,  H01L27/04 ,  H03K3/011 ,  H03K3/356 ,  H03K3/35 ,  H03K3/353 ,  H03L1/00

CPC分类号： G05F3/205 ,  G11C11/417 ,  H01L27/04 ,  H03K3/011 ,  H03K3/356008

摘要： A back gate bias voltage generator circuit consists of three MOS transistors (Q4, Q5, Q6) with a separate load element (Q1, Q2, Q3) coupled to the drain of each and a voltage clamp (Q7) connected to an output terminal (16). A terminal at the potential of a power supply (VCC) serves as one input and a terminal at the substrate potential (VSub) serves as another input. When the power supply (VCC) potential and the substrate potential are within normal operating ranges, the output terminal (16) assumes a reference potential (VSS). The potential of the output terminal increases in magnitude if either of the two input potentials (VSS, VSub) goes outside preselected operating ranges.

摘要翻译： 背栅偏置电压发生器电路由三个MOS晶体管（Q4，Q5，Q6）组成，具有耦合到每个的漏极的单独的负载元件（Q1，Q2，Q3）和连接到输出端子的电压钳（Q7） 16）。 电源电位（VCC）的端子用作一个输入，并且在衬底电位（VSub）上的端子用作另一个输入。 当电源（VCC）电位和衬底电位在正常工作范围内时，输出端（16）呈现参考电位（VSS）。 如果两个输入电位（VSS，VSub）中的任一个超出了预选的工作范围，输出端子的电位就会增加。