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    Polymer memory device and method of forming the same
    1.
    发明授权
    Polymer memory device and method of forming the same 有权
    聚合物记忆装置及其形成方法

    公开(公告)号：US08105697B2

    公开(公告)日：2012-01-31

    申请号：US11905510

    申请日：2007-10-02

    申请人： Byeong-Ok Cho ,  Takahiro Yasue ,  Moon-Sook Lee

    发明人： Byeong-Ok Cho ,  Takahiro Yasue ,  Moon-Sook Lee

    IPC分类号： B21D39/00 ,  B32B9/02

    CPC分类号： H01L27/285 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L51/0035 ,  H01L51/0047 ,  Y10T428/12556 ,  Y10T428/31681 ,  Y10T428/31721

    摘要： Provided is a polymer memory device and a method of forming the same. The polymer memory device may include a first electrode, a first curable polymer layer, a second electrode, a second curable polymer layer, and a third electrode. The first electrode may be disposed on a substrate. The first curable polymer layer may cover the first electrode. The second electrode may be disposed on the first curable polymer layer and cross over the first electrode. The second curable polymer layer may cover the second electrode. The third electrode may be disposed on the second curable polymer layer and cross over the second electrode. Each of the first curable polymer layer and the second curable polymer layer may contain a fullerene or a fullerene derivative.

    摘要翻译： 提供聚合物记忆装置及其形成方法。 聚合物记忆装置可以包括第一电极，第一可固化聚合物层，第二电极，第二可固化聚合物层和第三电极。 第一电极可以设置在基板上。 第一可固化聚合物层可以覆盖第一电极。 第二电极可以设置在第一可固化聚合物层上并与第一电极交叉。 第二可固化聚合物层可以覆盖第二电极。 第三电极可以设置在第二可固化聚合物层上并与第二电极交叉。 第一可固化聚合物层和第二可固化聚合物层中的每一个可以含有富勒烯或富勒烯衍生物。

    Thin film transistors
    2.
    发明授权
    Thin film transistors 有权
    薄膜晶体管

    公开(公告)号：US08022410B2

    公开(公告)日：2011-09-20

    申请号：US12497852

    申请日：2009-07-06

    申请人： Sang-Hun Jeon ,  Moon-Sook Lee ,  Byeong-Ok Cho

    发明人： Sang-Hun Jeon ,  Moon-Sook Lee ,  Byeong-Ok Cho

    IPC分类号： H01L29/786

    CPC分类号： H01L29/41733 ,  H01L27/1292 ,  H01L29/42384

    摘要： A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency.

    摘要翻译： 薄膜晶体管包括具有栅电极，栅极绝缘层和沟道层的层结构。 源极线可以接触沟道层，并且可以沿着与栅电极交叉的方向延伸。 源极线可以部分地与栅电极重叠，使得与栅电极重叠的源极线的两侧可以完全位于栅电极的两侧之间。 漏极线可以与沟道层接触并且可以与源极线隔开通道长度。 漏极线可以具有与源极线对称的结构。 可以减小栅电极，源极线和漏极线之间的重叠区域，使得薄膜晶体管可以确保高的截止频率。

    Phase changeable memory cells and methods of forming the same
    3.
    发明授权
    Phase changeable memory cells and methods of forming the same 有权
    相变存储单元及其形成方法

    公开(公告)号：US07642622B2

    公开(公告)日：2010-01-05

    申请号：US11288672

    申请日：2005-11-29

    申请人： Ji-Hye Yi ,  Byeong-Ok Cho ,  Sung-Lae Cho

    发明人： Ji-Hye Yi ,  Byeong-Ok Cho ,  Sung-Lae Cho

    IPC分类号： H01L29/22

    CPC分类号： H01L45/1233 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1675

    摘要： A phase changeable memory cell is provided. The phase changeable memory cell includes a lower interlayer dielectric layer formed on a semiconductor substrate and a lower conductive plug passing through the lower interlayer dielectric layer. The lower conductive plug is in contact with a phase change material pattern disposed on the lower interlayer dielectric layer. The phase change material pattern and the lower interlayer dielectric layer are covered with an upper interlayer dielectric layer. The phase change material pattern is in direct contact with a conductive layer pattern, which is disposed in a plate line contact hole passing through the upper interlayer dielectric layer. Methods of fabricating the phase changeable memory cell is also provided.

    摘要翻译： 提供了相变存储单元。 相变存储单元包括形成在半导体衬底上的下层间电介质层和通过下层间介电层的下导电插塞。 下导电插塞与布置在下层间介质层上的相变材料图案接触。 相变材料图案和下层间介电层被上层间介电层覆盖。 相变材料图案与布置在通过上层间介电层的板线接触孔中的导电层图案直接接触。 还提供了制造相变存储单元的方法。

    Methods of forming metal contact structures and methods of fabricating phase-change memory devices using the same
    4.
    发明授权
    Methods of forming metal contact structures and methods of fabricating phase-change memory devices using the same 有权
    形成金属接触结构的方法和使用其形成相变存储器件的方法

    公开(公告)号：US07622379B2

    公开(公告)日：2009-11-24

    申请号：US11084505

    申请日：2005-03-18

    申请人： Suk-Hun Choi ,  Byeong-ok Cho ,  Yoon-ho Son ,  Sang-don Nam

    发明人： Suk-Hun Choi ,  Byeong-ok Cho ,  Yoon-ho Son ,  Sang-don Nam

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76877 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

    摘要： Methods of forming a metal contact structure include forming an interlayer insulating layer on a substrate, etching the interlayer insulating layer to form a hole, depositing a metal layer on the surface of the interlayer insulating layer including inside the hole, planarizing the metal layer to provide a buried portion of the metal layer in the hole and to remove portions of the metal layer outside of the hole, etching-back the buried portion of the metal layer in the hole such that some of the portion of the metal layer within the hole remains and depositing a conductive layer on the surface of the interlayer insulating layer and the portion of the metal layer that remains within the hole. Methods of forming a phase change memory device are also provided.

    摘要翻译： 形成金属接触结构的方法包括在基板上形成层间绝缘层，蚀刻层间绝缘层以形成孔，在包括孔内部的层间绝缘层的表面上沉积金属层，平坦化金属层以提供 在孔中的金属层的掩埋部分并且去除孔的外部的金属层的部分，蚀刻孔中的金属层的掩埋部分，使得孔内的金属层的一些部分保持 以及在所述层间绝缘层的表面和所述金属层中保留在所述孔内的部分的表面上沉积导电层。 还提供了形成相变存储器件的方法。

    Biosensor using nanoscale material as transistor channel and method of fabricating the same
    5.
    发明申请
    Biosensor using nanoscale material as transistor channel and method of fabricating the same 有权
    使用纳米级材料作为晶体管沟道的生物传感器及其制造方法

    公开(公告)号：US20090085072A1

    公开(公告)日：2009-04-02

    申请号：US12232243

    申请日：2008-09-12

    申请人： Moon-Sook Lee ,  Byeong-Ok Cho ,  Man-Hyoung Ryoo ,  Takahiro Yasue ,  Jung-Hwan Hah

    发明人： Moon-Sook Lee ,  Byeong-Ok Cho ,  Man-Hyoung Ryoo ,  Takahiro Yasue ,  Jung-Hwan Hah

    IPC分类号： H01L21/28 ,  H01L29/772

    CPC分类号： G01N27/4145 ,  B82Y10/00 ,  B82Y15/00 ,  G01N27/4146 ,  H01L51/0595 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Example embodiments relate to a biosensor using a nanoscale material as a channel of a transistor and a method of fabricating the same. A biosensor according to example embodiments may include a plurality of insulating films. A first signal line and a second signal line may be interposed between the plurality of insulating films. A semiconductor nanostructure may be disposed on the plurality of insulating films, the semiconductor nanostructure having a first side electrically connected to the first signal line and a second side electrically connected to the second signal line. A plurality of probes may be coupled to the semiconductor nanostructure. A biosensor according to example embodiments may have a reduced analysis time.

    摘要翻译： 实施例涉及使用纳米级材料作为晶体管的沟道的生物传感器及其制造方法。 根据示例性实施例的生物传感器可以包括多个绝缘膜。 第一信号线和第二信号线可以插入在多个绝缘膜之间。 半导体纳米结构可以设置在多个绝缘膜上，半导体纳米结构具有电连接到第一信号线的第一侧和与第二信号线电连接的第二侧。 多个探针可以耦合到半导体纳米结构。 根据示例性实施例的生物传感器可以具有减少的分析时间。

    Polymer memory device and method of forming the same
    6.
    发明申请
    Polymer memory device and method of forming the same 有权
    聚合物记忆装置及其形成方法

    公开(公告)号：US20080131712A1

    公开(公告)日：2008-06-05

    申请号：US11905510

    申请日：2007-10-02

    申请人： Byeong-Ok Cho ,  Takahiro Yasue ,  Moon-Sook Lee

    发明人： Byeong-Ok Cho ,  Takahiro Yasue ,  Moon-Sook Lee

    IPC分类号： B32B27/06 ,  B05D5/12

    CPC分类号： H01L27/285 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L51/0035 ,  H01L51/0047 ,  Y10T428/12556 ,  Y10T428/31681 ,  Y10T428/31721

    摘要： Provided is a polymer memory device and a method of forming the same. The polymer memory device may include a first electrode, a first curable polymer layer, a second electrode, a second curable polymer layer, and a third electrode. The first electrode may be disposed on a substrate. The first curable polymer layer may cover the first electrode. The second electrode may be disposed on the first curable polymer layer and cross over the first electrode. The second curable polymer layer may cover the second electrode. The third electrode may be disposed on the second curable polymer layer and cross over the second electrode. Each of the first curable polymer layer and the second curable polymer layer may contain a fullerene or a fullerene derivative.

    摘要翻译： 提供聚合物记忆装置及其形成方法。 聚合物记忆装置可以包括第一电极，第一可固化聚合物层，第二电极，第二可固化聚合物层和第三电极。 第一电极可以设置在基板上。 第一可固化聚合物层可以覆盖第一电极。 第二电极可以设置在第一可固化聚合物层上并与第一电极交叉。 第二可固化聚合物层可以覆盖第二电极。 第三电极可以设置在第二可固化聚合物层上并与第二电极交叉。 第一可固化聚合物层和第二可固化聚合物层中的每一个可以含有富勒烯或富勒烯衍生物。

    Phase changeable memory cells and methods of forming the same
    9.
    发明申请
    Phase changeable memory cells and methods of forming the same 有权
    相变存储单元及其形成方法

    公开(公告)号：US20060118913A1

    公开(公告)日：2006-06-08

    申请号：US11288672

    申请日：2005-11-29

    申请人： Ji-Hye Yi ,  Byeong-Ok Cho ,  Sung-Lae Cho

    发明人： Ji-Hye Yi ,  Byeong-Ok Cho ,  Sung-Lae Cho

    IPC分类号： H01L21/00 ,  H01L29/12

    CPC分类号： H01L45/1233 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1675

    摘要： A phase changeable memory cell is provided. The phase changeable memory cell includes a lower interlayer dielectric layer formed on a semiconductor substrate and a lower conductive plug passing through the lower interlayer dielectric layer. The lower conductive plug is in contact with a phase change material pattern disposed on the lower interlayer dielectric layer. The phase change material pattern and the lower interlayer dielectric layer are covered with an upper interlayer dielectric layer. The phase change material pattern is in direct contact with a conductive layer pattern, which is disposed in a plate line contact hole passing through the upper interlayer dielectric layer. Methods of fabricating the phase changeable memory cell is also provided.

    摘要翻译： 提供了相变存储单元。 相变存储单元包括形成在半导体衬底上的下层间电介质层和通过下层间介电层的下导电插塞。 下导电插塞与布置在下层间介质层上的相变材料图案接触。 相变材料图案和下层间介电层被上层间介电层覆盖。 相变材料图案与布置在通过上层间介电层的板线接触孔中的导电层图案直接接触。 还提供了制造相变存储单元的方法。

    Methods of fabricating phase changeable semiconductor memory devices including multi-plug conductive structures and related devices
    10.
    发明申请
    Methods of fabricating phase changeable semiconductor memory devices including multi-plug conductive structures and related devices 审中-公开
    制造包括多插头导电结构和相关装置的相变半导体存储器件的方法

    公开(公告)号：US20060076641A1

    公开(公告)日：2006-04-13

    申请号：US11209938

    申请日：2005-08-23

    申请人： Byeong-Ok Cho ,  Sang-Don Nam ,  Suk-Hun Choi

    发明人： Byeong-Ok Cho ,  Sang-Don Nam ,  Suk-Hun Choi

    IPC分类号： H01L29/40 ,  H01L21/44

    CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675

    摘要： In fabricating a phase changeable memory device, an insulating layer with an opening extending therethrough is formed on a substrate. A conductive structure is formed in the opening. The conductive structure includes a first conductive plug on opposing sidewalls of the opening and a surface therebetween and a second plug on the first conductive plug. The first conductive plug is between the second plug and the sidewalls of the opening and between the second plug and the surface therebetween. A lower electrode is formed on the first conductive plug, on the second plug, and on the insulating layer. The lower electrode extends outside the opening in the insulating layer. A phase changeable material layer is formed on the lower electrode, and an upper electrode is formed on the phase changeable material layer opposite the lower electrode.

    摘要翻译： 在制造相变存储器件时，在衬底上形成具有延伸通过其的开口的绝缘层。 在开口中形成导电结构。 导电结构包括位于开口的相对侧壁上的第一导电插塞和其间的表面，以及在第一导电插塞上的第二插头。 第一导电插头位于第二插头和开口的侧壁之间以及第二插头与它们之间的表面之间。 下电极形成在第一导电插塞上，第二插头上，绝缘层上。 下电极延伸到绝缘层的开口的外侧。 在下电极上形成相变材料层，在与下电极相对的相变材料层上形成上电极。