公开(公告)号：US20120211863A1

公开(公告)日：2012-08-23

申请号：US13456079

申请日：2012-04-25

Applicant: Ting Cheong Ang

Inventor： Ting Cheong Ang

IPC: H01L29/06

CPC classification number: H01L21/76224

Abstract: A semiconductor structure includes a semiconductor substrate with a substrate region and a trench extending into the surface region of the semiconductor substrate. The trench includes sidewalls, a bottom and a depth. The semiconductor structure further includes a trench liner overlying the bottom and the sidewalls of the trench. The semiconductor structure also includes a shallow trench isolation structure filling at least the depth of the trench. The shallow trench isolation structure is formed from alternating layers of silicon nitride and high-density plasma oxide.

Abstract translation: 半导体结构包括具有衬底区域的半导体衬底和延伸到半导体衬底的表面区域中的沟槽。 沟槽包括侧壁，底部和深度。 半导体结构还包括覆盖沟槽的底部和侧壁的沟槽衬垫。 半导体结构还包括至少填充沟槽的深度的浅沟槽隔离结构。 浅沟槽隔离结构由氮化硅和高密度等离子体氧化物的交替层形成。

公开(公告)号：US08187950B2

公开(公告)日：2012-05-29

申请号：US12258366

申请日：2008-10-24

Applicant: Ting Cheong Ang

Inventor： Ting Cheong Ang

IPC: H01L21/76

CPC classification number: H01L21/76224

Abstract: A method of forming a semiconductor structure is provided. The method includes providing a semiconductor substrate with a substrate region. The method also includes forming a pad oxide layer overlying the substrate region. The method additionally includes forming a stop layer overlying the pad oxide layer. Furthermore, the method includes patterning the stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a height. Also, the method includes depositing alternating layers of oxide and silicon nitride to at least fill the trench, the oxide being deposited by an HDP-CVD process. The method additionally includes performing a planarization process to remove a portion of the silicon nitride and oxide layers. In addition, the method includes removing the pad oxide and stop layers.

Abstract translation: 提供一种形成半导体结构的方法。 该方法包括提供具有衬底区域的半导体衬底。 该方法还包括形成覆盖衬底区域的衬垫氧化物层。 该方法还包括形成覆盖衬垫氧化物层的阻挡层。 此外，该方法包括图案化停止层和衬垫氧化物层以暴露衬底区域的一部分。 此外，该方法包括在衬底区域的暴露部分内形成沟槽，沟槽具有侧壁，底部和高度。 此外，该方法包括沉积氧化物和氮化硅的交替层以至少填充沟槽，氧化物通过HDP-CVD工艺沉积。 该方法另外包括执行平坦化处理以去除一部分氮化硅和氧化物层。 此外，该方法包括去除衬垫氧化物并停止层。

公开(公告)号：US20090075454A1

公开(公告)日：2009-03-19

申请号：US12273323

申请日：2008-11-18

Applicant: Ting Cheong Ang

Inventor： Ting Cheong Ang

IPC: H01L21/76

CPC classification number: H01L21/76224

Abstract: A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench.

Abstract translation: 提供了一种用于半导体器件的STI间隙填充处理的方法。 在本发明的具体实施方案中，该方法包括形成覆盖衬底的阻挡层。 此外，该方法包括在衬底内形成沟槽，其中沟槽具有侧壁，底部和深度。 该方法还包括在沟槽内形成衬垫，衬垫衬在沟槽的侧壁和底部。 此外，该方法包括用第一氧化物将沟槽填充到第一深度。 使用旋涂工艺填充第一氧化物。 该方法还包括对沟槽内的第一氧化物进行第一致密化处理。 另外，该方法包括使用HDP工艺在沟槽内沉积第二氧化物以填充至少整个沟槽。 该方法还包括对沟槽内的第一和第二氧化物进行第二致密化处理。

公开(公告)号：US20070254453A1

公开(公告)日：2007-11-01

申请号：US11549116

申请日：2006-10-13

Applicant: Ting Cheong Ang

Inventor： Ting Cheong Ang

IPC: H01L21/76

CPC classification number: H01L21/76232

Abstract: A method of forming a graded trench for a shallow trench isolation region is provided. The method includes providing a semiconductor substrate with a substrate region. The method further includes forming a pad oxide layer overlying the substrate region. Additionally, the method includes forming an etch stop layer overlying the pad oxide layer. The method further includes patterning the etch stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a first depth. The method additionally includes forming a dielectric layer overlying the trench sidewalls, the trench bottom, and mesa regions adjacent to the trench. The method further includes removing a first portion of the dielectric layer from the trench bottom to expose the substrate region with a second portion of the dielectric layer remaining on the sidewalls of the trench. In addition, the method includes etching the substrate region to increase the depth of at least a portion of the trench to a second depth. Also, the method includes removing the second portion of the dielectric layer from the trench.

Abstract translation: 提供了形成浅沟槽隔离区域的分级沟槽的方法。 该方法包括提供具有衬底区域的半导体衬底。 该方法还包括形成覆盖衬底区域的衬垫氧化物层。 另外，该方法包括形成覆盖衬垫氧化物层的蚀刻停止层。 该方法还包括图案化蚀刻停止层和衬垫氧化物层以暴露衬底区域的一部分。 此外，该方法包括在衬底区域的暴露部分内形成沟槽，沟槽具有侧壁和底部以及第一深度。 该方法另外包括形成覆盖沟槽侧壁，沟槽底部和与沟槽相邻的台面区域的介电层。 该方法还包括从沟槽底部去除电介质层的第一部分以暴露衬底区域，其中介电层的第二部分保留在沟槽的侧壁上。 此外，该方法包括蚀刻衬底区域以将沟槽的至少一部分的深度增加到第二深度。 此外，该方法包括从沟槽去除电介质层的第二部分。

公开(公告)号：US06963113B2

公开(公告)日：2005-11-08

申请号：US10915670

申请日：2004-08-10

Applicant: Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek ,  Jun Song

Inventor： Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek ,  Jun Song

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/76

CPC classification number: H01L29/66772 ,  H01L29/78615

Abstract: A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. A second contact opening is made through the interlevel dielectric layer in each of the active regions wherein the second contact opening contacts both the first trench and one of the second trenches. The first and second contact openings are filled with a conducting layer to complete formation of a silicon-on-insulator device in the fabrication of integrated circuits.

Abstract translation: 描述了一种在消除浮体效应的同时形成绝缘体上硅MOSFET的新方法。 提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下面的硅半导体衬底。 第一沟槽部分地被蚀刻穿过硅层而不是蚀刻到下面的氧化物层。 第二沟槽被完全蚀刻通过硅层到下面的氧化物层，其中第二沟槽分离半导体衬底的有源区域，并且其中第一沟槽中的一个位于每个有源区域内。 第一和第二沟槽填充有绝缘层。 栅极电极和相关的源极和漏极区域形成在每个有源区域中的硅层中和硅层上。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 在每个有源区域中通过层间电介质层形成第二接触开口，其中第二接触开口接触第一沟槽和第二沟槽中的一个沟槽。 第一和第二接触开口填充有导电层，以在集成电路的制造中完成绝缘体上硅器件的形成。

公开(公告)号：US06815823B2

公开(公告)日：2004-11-09

申请号：US10679736

申请日：2003-10-06

Applicant: Young-Way Teh ,  Victor Seng Keong Lim ,  Ting Cheong Ang

Inventor： Young-Way Teh ,  Victor Seng Keong Lim ,  Ting Cheong Ang

IPC: H01L2348

CPC classification number: H01L23/5226 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76804 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.

Abstract translation: 提供了一种新的方法和结构来创建互连线。 在与互连线的纵向方向垂直的平面中截取的本发明的互连线的横截面是与传统的互连线的矩形或矩形横截面相反的三角形。

公开(公告)号：US06582856B1

公开(公告)日：2003-06-24

申请号：US09513872

申请日：2000-02-28

Applicant: Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Song ,  Sang Yee Loong

Inventor： Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Song ,  Sang Yee Loong

IPC: G03F900

CPC classification number: G03F1/29

Abstract: A new method of fabricating a rim phase shifting mask is achieved. An opaque layer is provided overlying a transparent substrate. A resist layer is deposited overlying the opaque layer. The resist layer is patterned. The opaque layer and the transparent substrate are etched. The resist layer masks this etching. The opaque layer is etched through during this etching. Notches are thereby etched into the transparent substrate at the edges of the opaque layer. These notches will cause a phase shift in incident light relative to incident light passing through regions in the transparent substrate adjacent to the notches. During this etching, an overetch is performed to remove any mask defects in the transparent substrate. Optionally, the notches may be etched into a phase shifting layer overlying the transparent substrate. An etch stopping layer may also be used in the phase shifting layer embodiment.

Abstract translation: 实现了制作边缘相移掩模的新方法。 在透明基底上方设置不透明层。 将抗蚀剂层沉积在不透明层上。 抗蚀剂层被图案化。 蚀刻不透明层和透明基板。 抗蚀剂层掩盖该蚀刻。 在该蚀刻期间蚀刻不透明层。 因此，在不透明层的边缘处，凹口被蚀刻到透明基板中。 这些凹口将引起入射光相对于穿过透明衬底中与凹口相邻的区域的入射光的相移。 在该蚀刻期间，执行过蚀刻以去除透明基板中的任何掩模缺陷。 可选地，凹口可被蚀刻到覆盖透明衬底的相移层中。 在相移层实施例中也可以使用蚀刻停止层。

公开(公告)号：US06492726B1

公开(公告)日：2002-12-10

申请号：US09667837

申请日：2000-09-22

Applicant: Shyue Fong Quek ,  Ying Keung Leung ,  Sang Yee Loong ,  Ting Cheong Ang

Inventor： Shyue Fong Quek ,  Ying Keung Leung ,  Sang Yee Loong ,  Ting Cheong Ang

IPC: H01L2348

CPC classification number: H01L23/36 ,  H01L23/055 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In accordance with the objectives of the invention a new package is provided that is provided with a cavity that is shaped such that more than one semiconductor device can in a vertical direction be mounted in the cavity of the package. The devices that are mounted inside the cavity of the package are separated by separate components of insulation, the overlying devices are electrically interconnected by horizontally positioned solder bumps and vertical interconnect plugs.

Abstract translation: 根据本发明的目的，提供了一种新的封装，其具有形成使得多于一个半导体器件可以在垂直方向上可以安装在封装的空腔中的空腔。 安装在封装腔内的器件由绝缘体的分开的部件隔开，上覆的器件通过水平定位的焊料凸块和垂直互连插头电互连。

公开(公告)号：US06406948B1

公开(公告)日：2002-06-18

申请号：US09615807

申请日：2000-07-13

Applicant: Song Jun ,  Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek

Inventor： Song Jun ,  Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek

IPC: H01L2184

CPC classification number: H01L27/0251 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. An N-well is formed within a silicon semiconductor substrate. A P+ region is implanted within a portion of the N-well and an N+ region is implanted within a portion of the semiconductor substrate not occupied by the N-well. An oxide layer is formed overlying the semiconductor substrate and patterned to form openings to the semiconductor substrate. An epitaxial silicon layer is grown within the openings and overlying the oxide layer. Shallow trench isolation regions are formed within the epitaxial silicon layer extending to the underlying oxide layer. Gate electrodes and associated source and drain regions are formed in and on the epitaxial silicon layer between the shallow trench isolation regions. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. The interlevel dielectric layer is covered with a mask that covers the first contact openings. Second contact openings are opened through the interlevel dielectric layer, shallow trench isolations, and the oxide layer to the N+ region and P+ region. The mask is removed. The first and second contact openings are filled with a conducting layer to complete formation of an ESD device.

Abstract translation: 描述了使用绝缘体上硅技术形成静电放电装置的方法。 在硅半导体衬底内形成N阱。 将P +区注入到N阱的一部分内，并且将N +区注入到不被N阱占据的半导体衬底的一部分内。 在半导体衬底上形成氧化物层并图案化以形成到半导体衬底的开口。 外延硅层生长在开口内并覆盖氧化物层。 在延伸到下面的氧化物层的外延硅层内形成浅沟槽隔离区。 在浅沟槽隔离区域之间的外延硅层中和栅极电极和相关的源极和漏极区域上形成栅电极。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 用覆盖第一接触开口的掩模覆盖层间电介质层。 第二接触开口通过层间介质层，浅沟槽隔离层和氧化物层开放到N +区域和P +区域。 去除面具。 第一和第二接触开口填充有导电层以完成ESD装置的形成。

公开(公告)号：US06376319B2

公开(公告)日：2002-04-23

申请号：US09972629

申请日：2001-10-09

Applicant: Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

Inventor： Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

Abstract: A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions. Additional iterations include the use of an L shaped spacer, overlying the source/drain extension region, as well as the formation of metal silicide, on the doped SEG silicon regions, and on the gate structures.

Abstract translation: 已经开发了一种用于制造MOSFET器件的方法，其特征在于在利用高温工艺（例如重掺杂源极/漏极区域）之后形成的源极/漏极延伸区域。 在掺杂的SEG硅区域的侧面上形成一次性绝缘体间隔物，随后在位于掺杂的SEG硅区域之间的半导体衬底的区域上形成栅极绝缘体层和覆盖栅极结构。 在这些工艺步骤中经历的温度导致SEG硅区域下方的重掺杂源极/漏极的形成。 选择性地去除一次性间隔件允许源极/漏极延伸区域被放置在与重掺杂的源极/漏极区域相邻的由一次性间隔物空出的空间中。 然后使用绝缘体间隔物来填充通过去除一次性间隔件而空出的空间，直接覆盖源极/漏极延伸区域。 另外的迭代包括在掺杂的SEG硅区域上以及栅极结构上使用覆盖源极/漏极延伸区域的L形间隔物以及金属硅化物的形成。