公开(公告)号：US20120231573A1

公开(公告)日：2012-09-13

申请号：US13479189

申请日：2012-05-23

Applicant: YANG WU ,  CHI-SHAO LIN

Inventor： YANG WU ,  CHI-SHAO LIN

IPC: H01L31/18

CPC classification number: H01L27/14687 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14643

Abstract: A process and structure of a backside illumination (BSI) image sensor are disclosed. An n-type doped region is formed in a substrate, and a transfer gate is formed on top of the semiconductor substrate. A p-type doped region is formed in the n-type doped region either using the transfer gate as a mask or is non-self aligned formed.

Abstract translation: 公开了背照明（BSI）图像传感器的处理和结构。 在衬底中形成n型掺杂区域，并且在半导体衬底的顶部上形成传输栅极。 在n型掺杂区域中，使用传输栅极作为掩模形成p型掺杂区域，或者形成非自对准区域。

公开(公告)号：US08253827B2

公开(公告)日：2012-08-28

申请号：US12555654

申请日：2009-09-08

Applicant: Chih-Min Liu ,  Amit Mittra ,  Chi-Shao Lin

Inventor： Chih-Min Liu ,  Amit Mittra ,  Chi-Shao Lin

IPC: H04N9/64 ,  H04N5/235 ,  H04N5/228

CPC classification number: H04N5/361

Abstract: A signal chain of an imaging system is disclosed. The system includes three circuit stages. The first circuit stage includes a programmable gain amplifier (PGA) and a black level compensation (BLC) circuit that form a BLC loop. The second circuit stage includes an analog-to-digital converter (ADC), where a dark signal offset is added at an input of the ADC. The third circuit stage includes a digital gain circuit and a digital loop that makes a final output of the imaging system settle on a target level in the BLC mode.

Abstract translation: 公开了一种成像系统的信号链。 该系统包括三个电路级。 第一电路级包括形成BLC回路的可编程增益放大器（PGA）和黑电平补偿（BLC）电路。 第二电路级包括模数转换器（ADC），其中在ADC的输入处加上暗信号偏移。 第三电路级包括数字增益电路和使得成像系统的最终输出在BLC模式下达到目标电平的数字环路。

公开(公告)号：US20110169055A1

公开(公告)日：2011-07-14

申请号：US12795256

申请日：2010-06-07

Applicant: YANG WU ,  CHI-SHAO LIN

Inventor： YANG WU ,  CHI-SHAO LIN

IPC: H01L31/10 ,  H01L31/18 ,  H01L31/0352

CPC classification number: H01L27/14687 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14643

Abstract: A process and structure of a back side illumination (BSI) image sensor are disclosed. An n-type doped region is formed in a substrate, and a transfer gate is formed on top of the semiconductor substrate. A p-type doped region is formed in the n-type doped region either using the transfer gate as a mask or is non-self aligned formed.

Abstract translation: 公开了背面照明（BSI）图像传感器的处理和结构。 在衬底中形成n型掺杂区，并且在半导体衬底的顶部上形成传输栅。 在n型掺杂区域中，使用传输栅极作为掩模形成p型掺杂区域，或者形成非自对准区域。

公开(公告)号：US20100283878A1

公开(公告)日：2010-11-11

申请号：US12464079

申请日：2009-05-11

Applicant: Chi-Shao Lin

Inventor： Chi-Shao Lin

IPC: H04N5/335

CPC classification number: H04N5/378 ,  H04N5/35554 ,  H04N5/374

Abstract: A scheme is provided that enhances the dynamic range performance of images via multiple readouts during one exposure. The readout process circuit structure includes at least an analog-to-digital converter (ADC). The analog-to-digital converter converts analog data generated from an image sensor into digital data, allowing sub-frame readouts for improving a dynamic range of the image sensor. Additionally, methods of partial digitization (not a full number of bits) and image array are provided.

Abstract translation: 提供了一种在一次曝光期间通过多个读出增强图像的动态范围性能的方案。 读出过程电路结构至少包括一个模拟 - 数字转换器（ADC）。 模数转换器将从图像传感器生成的模拟数据转换为数字数据，允许子帧读数，以改善图像传感器的动态范围。 另外，提供了部分数字化（不是全数位）和图像阵列的方法。

公开(公告)号：US20100282946A1

公开(公告)日：2010-11-11

申请号：US12436045

申请日：2009-05-05

Applicant: Ping-Hung Yin ,  Amit Mittra ,  Chi-Shao Lin

Inventor： Ping-Hung Yin ,  Amit Mittra ,  Chi-Shao Lin

IPC: H03F3/08 ,  H01L27/00

CPC classification number: H03F3/08 ,  H01L27/14643 ,  H04N5/3559

Abstract: A pixel circuit of a CMOS image sensor is disclosed. At least two transfer transistors are configured to transfer integrated light signals of corresponding photodetectors to a first node. A reset transistor is configured to reset the first node to a predetermined reset voltage of a second node, and a source follower is configured to buffer the integrated light signals. In one embodiment, a capacitor is further connected between the first node and the second node to minimize influence of the effective capacitance including capacitance of a floating diffusion region and parasitic capacitance due to the photodetector and the transfer transistor.

Abstract translation: 公开了CMOS图像传感器的像素电路。 至少两个传输晶体管被配置为将相应光电检测器的集成光信号传送到第一节点。 复位晶体管被配置为将第一节点复位到第二节点的预定复位电压，并且源跟随器被配置为缓冲集成光信号。 在一个实施例中，电容器还被连接在第一节点和第二节点之间，以最小化包括浮动扩散区域的电容和由于光电检测器和传输晶体管引起的寄生电容的有效电容的影响。

公开(公告)号：US20090295965A1

公开(公告)日：2009-12-03

申请号：US12129900

申请日：2008-05-30

Applicant: Desmond Yu Hin Cheung ,  Amit Mittra ,  Chi-Shao Lin

Inventor： Desmond Yu Hin Cheung ,  Amit Mittra ,  Chi-Shao Lin

IPC: H04N5/335 ,  H01L27/146

CPC classification number: H04N5/3745 ,  H01L27/14641 ,  H04N5/357

Abstract: One embodiment of the present invention describes a pixel circuit that comprises at least one photodiode, a first transistor coupled between the photodiode and a floating diffusion node, a second transistor coupled between the floating diffusion node and a modifiable driving voltage signal, and a third transistor having a gate coupled to the floating diffusion node, a source coupled to a signal output, and a drain coupled to a constant voltage. Another embodiment of the present invention provides a method for driving the pixel circuit, which comprises resetting the photodiode and the floating diffusion node, exposing the photodiode to light to accumulate charges, selecting the pixel circuit by switching the driving voltage signal from a first voltage level to a second voltage level, retrieving a reference voltage from the selected pixel circuit, and retrieving an image signal from the selected pixel circuit corresponding to the accumulated charges.

Abstract translation: 本发明的一个实施例描述了一种像素电路，其包括至少一个光电二极管，耦合在光电二极管和浮动扩散节点之间的第一晶体管，耦合在浮动扩散节点和可修改驱动电压信号之间的第二晶体管，以及第三晶体管 具有耦合到浮动扩散节点的栅极，耦合到信号输出的源极和耦合到恒定电压的漏极。 本发明的另一个实施例提供了一种用于驱动像素电路的方法，该方法包括复位光电二极管和浮动扩散节点，将光电二极管暴露于​​光以累积电荷，通过从第一电压电平切换驱动电压信号来选择像素电路 获取第二电压电平，从所选择的像素电路检索参考电压，以及从对应于累积电荷的所选择的像素电路中检索图像信号。

公开(公告)号：US20070001101A1

公开(公告)日：2007-01-04

申请号：US11238425

申请日：2005-09-28

Applicant: Raj Sundararaman ,  Chi-Shao Lin ,  Jiafu Luo ,  Richard Mann ,  Zeynep Toros

Inventor： Raj Sundararaman ,  Chi-Shao Lin ,  Jiafu Luo ,  Richard Mann ,  Zeynep Toros

IPC: H01J40/14

CPC classification number: H04N5/335 ,  H04N5/3745 ,  H04N5/376

Abstract: An electronic device is provided such as a programmable rise/fall time control circuit, for example, that delivers a continuous and near linear rising/falling slope of a control signal, with programmability that can be implemented in future CMOS image sensor devices. This device includes a programmability block for reset or transfer gate signals. The programmability block includes two inputs: an input bias current and a signal from the control bits. The programmability block further includes two similar internal circuit blocks, one for generating a fall time control signal, and one for generating a rise time control signal. Additionally the programmability block includes two outputs; a fall time control signal, and a rise time control signal. The device further includes a reset or transfer gate buffer configured as an inverter. The reset or transfer gate buffer includes three input signals: The fall time control signal and rise time control signal from the programmability block, and an INT Reset signal. Furthermore, the reset or transfer gate buffer includes an output reset or transfer gate signal. The device is configured to take an input bias current, and by controlling the transconductance of internal circuitry provide a tapered rise and fall time signal to a reset or transfer gate of a CMOS image sensor that is programmable.

Abstract translation: 提供了诸如可编程上升/下降时间控制电路的电子装置，其可以传递控制信号的连续和近似线性的上升/下降斜率，具有可在将来的CMOS图像传感器装置中实现的可编程性。 该器件包括用于复位或传输门信号的可编程块。 可编程块包括两个输入：输入偏置电流和来自控制位的信号。 可编程块还包括两个类似的内部电路块，一个用于产生下降时间控制信号，另一个用于产生上升时间控制信号。 此外，可编程块包括两个输出; 下降时间控制信号和上升时间控制信号。 该装置还包括被配置为反相器的复位或传输门缓冲器。 复位或传输门缓冲器包括三个输入信号：来自可编程块的下降时间控制信号和上升时间控制信号，以及一个INT复位信号。 此外，复位或传输门缓冲器包括输出复位或传输门信号。 该器件被配置为获取输入偏置电流，并且通过控制内部电路的跨导向可编程的CMOS图像传感器的复位或传输门提供渐变的上升和下降时间信号。

公开(公告)号：US08564697B2

公开(公告)日：2013-10-22

申请号：US12582715

申请日：2009-10-21

Applicant: Nguyen Dong ,  Amit Mittra ,  Chi-Shao Lin

Inventor： Nguyen Dong ,  Amit Mittra ,  Chi-Shao Lin

IPC: H04N9/64

CPC classification number: H04N5/361 ,  H04N5/335

Abstract: Black level calibration methods and systems are generally disclosed. According to one embodiment of the present invention, a method of calibrating a black level signal in a frame includes performing an iteration of averaging a first set of digital values corresponding to a first set of adjusted black level signals associated with a first set of black pixels of the frame, determining whether an average value based on the first set of digital values has reached a target black level, determining a calibration offset based on a difference between the average value and the target black level and an accumulator step, converting the calibration offset to an analog signal, generating a calibration signal based on the analog signal for a second set of black pixels of the frame, and repeating the iteration for the frame until a predetermined condition is determined to have been met.

Abstract translation: 通常公开黑电平校准方法和系统。 根据本发明的一个实施例，一种在帧中校准黑电平信号的方法包括执行对与第一组黑色像素相关联的第一组经调整的黑电平信号相对应的第一组数字值进行平均的迭代 确定基于第一组数字值的平均值是否已经达到目标黑电平，基于平均值和目标黑电平之间的差确定校准偏移和累加器步骤，将校准偏移转换 模拟信号，基于该帧的第二组黑色像素的模拟信号产生校准信号，并重复该帧的迭代，直到确定已经满足预定条件。

公开(公告)号：US08237207B2

公开(公告)日：2012-08-07

申请号：US12795256

申请日：2010-06-07

Applicant: Yang Wu ,  Chi-Shao Lin

Inventor： Yang Wu ,  Chi-Shao Lin

IPC: H01L31/062

CPC classification number: H01L27/14687 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14643

Abstract: A process and structure of a back side illumination (BSI) image sensor are disclosed. An n-type doped region is formed in a substrate, and a transfer gate is formed on top of the semiconductor substrate. A p-type doped region is formed in the n-type doped region either using the transfer gate as a mask or is non-self aligned formed.

Abstract translation: 公开了背面照明（BSI）图像传感器的处理和结构。 在衬底中形成n型掺杂区，并且在半导体衬底的顶部上形成传输栅。 在n型掺杂区域中，使用传输栅极作为掩模形成p型掺杂区域，或者形成非自对准区域。

公开(公告)号：US20120080766A1

公开(公告)日：2012-04-05

申请号：US12898419

申请日：2010-10-05

Applicant: Chung-Wei Chang ,  Fang-Ming Huang ,  Chi-Shao Lin ,  Yu-Ping Hu

Inventor： Chung-Wei Chang ,  Fang-Ming Huang ,  Chi-Shao Lin ,  Yu-Ping Hu

IPC: H01L27/146 ,  H01L31/18

CPC classification number: H01L31/18 ,  H01L27/14621 ,  H01L27/1463 ,  H01L27/14645 ,  H01L27/14689

Abstract: An image sensing device is disclosed, including an epitaxy layer having the a conductivity type, including a first pixel area corresponding to a first incident light, a second pixel area corresponding to a second incident light, and a third pixel area corresponding to a third incident light, wherein the wavelength of the first incident light is longer than that of the second incident light and the wavelength of the second incident light is longer than that of the third incident light. A photodiode is disposed in an upper portion of the epitaxy layer, and a first deep well for reducing pixel-to-pixel talk of the image sensing device is disposed in a lower portion of the epitaxy layer in the second pixel area and the third pixel area, wherein at least a portion of the epitaxy layer in first pixel area does not include the first deep well.

Abstract translation: 公开了一种图像感测装置，包括具有导电类型的外延层，包括对应于第一入射光的第一像素区域，对应于第二入射光的第二像素区域和对应于第三入射光的第三像素区域 光，其中第一入射光的波长比第二入射光的波长长，第二入射光的波长比第三入射光的波长长。 光电二极管设置在外延层的上部，并且用于减少图像感测装置的像素到像素的通话的第一深阱设置在第二像素区域中的外延层的下部和第三像素 区域，其中第一像素区域中的外延层的至少一部分不包括第一深孔。