公开(公告)号：US08356221B2

公开(公告)日：2013-01-15

申请号：US12861991

申请日：2010-08-24

申请人： Mark T. Kuo ,  Michael Howard ,  Daniel C. Murray

发明人： Mark T. Kuo ,  Michael Howard ,  Daniel C. Murray

IPC分类号： G01R31/28

CPC分类号： G01R31/31858 ,  G01R31/318544 ,  G11C29/32

摘要： A method and apparatus for conducting transition testing using scan elements are disclosed. In one embodiment, an integrated circuit (IC) includes a scan chain having first and second subsets of scannable flops, the first subset having respective data inputs coupled to a memory array. The scannable flops of the second subset may each have a respective data input coupled to circuitry other than the memory array (e.g., to a logic circuit). The scannable flops of the first subset may be enabled for scan shifting during a transition test mode. The scannable flops of the second subset are inhibited from scanning during the transition test mode. The transition test mode may include at least two functional clock cycles in which the scannable flops of the first subset provide complementary first and second logic values to logic circuits coupled to respective data outputs.

摘要翻译： 公开了一种使用扫描元件进行转换测试的方法和装置。 在一个实施例中，集成电路（IC）包括具有可扫描触发器的第一和第二子集的扫描链，第一子集具有耦合到存储器阵列的相应数据输入。 第二子集的可扫描触发器可以各自具有耦合到除了​​存储器阵列之外的电路（例如，到逻辑电路）的相应数据输入。 在转换测试模式期间，可以启用第一子集的可扫描的触发器用于扫描移位。 在转换测试模式期间禁止第二子集的可扫描触发器扫描。 转换测试模式可以包括至少两个功能时钟周期，其中第一子集的可扫描触发器为耦合到相应数据输出的逻辑电路提供互补的第一和第二逻辑值。

公开(公告)号：US20120290818A1

公开(公告)日：2012-11-15

申请号：US13557725

申请日：2012-07-25

申请人： Andrew J. Beaumont-Smith ,  Honkai Tam ,  Daniel C. Murray ,  John H. Mylius ,  Peter J. Bannon ,  Pradeep Kanapathipillai

发明人： Andrew J. Beaumont-Smith ,  Honkai Tam ,  Daniel C. Murray ,  John H. Mylius ,  Peter J. Bannon ,  Pradeep Kanapathipillai

IPC分类号： G06F9/30

CPC分类号： G06F9/3838 ,  G06F9/384 ,  G06F9/3857

摘要： In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.

摘要翻译： 在一个实施例中，调度器实现第一依赖性数组，其跟踪给定操作的距离N内的指令操作（操作）的依赖性，并且其是短执行延迟操作。 其他依赖关系在第二个依赖关系数组中被跟踪。 第一个依赖数组可以快速评估，以支持短执行延迟操作及其依赖操作的背对背发布。 第二个数组可能比第一个依赖数组慢得多。

公开(公告)号：US07760559B2

公开(公告)日：2010-07-20

申请号：US12325476

申请日：2008-12-01

申请人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

发明人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC分类号： G11C7/00

CPC分类号： G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

摘要： In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

摘要翻译： 在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。 即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。 在另一个实施例中，一种方法包括读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

公开(公告)号：US20100169619A1

公开(公告)日：2010-07-01

申请号：US12721164

申请日：2010-03-10

申请人： Tse-yu Yeh ,  Daniel C. Murray ,  Po Yung Chang ,  Anup S. Mehta

发明人： Tse-yu Yeh ,  Daniel C. Murray ,  Po Yung Chang ,  Anup S. Mehta

IPC分类号： G06F9/305 ,  G06F12/08 ,  G06F12/00 ,  G06F9/00

CPC分类号： G06F12/0607

摘要： In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation. The first even mask identifies bytes within the first even byte range that are written by the store memory operation, and wherein the first odd mask identifies bytes within the first odd byte range that are written by the store memory operation.

摘要翻译： 在一个实施例中，装置包括包括多个条目的队列和耦合到队列的控制单元。 控制单元被配置为将第一队列条目分配给存储存储器操作，并且被配置为将对应于存储存储器操作的第一偶数偏移，第一偶数掩码，第一奇数偏移和第一奇数掩码写入到 第一次入场 一组连续的存储器位置在逻辑上被划分为交替寻址的偶数和奇数字节范围。 给定的存储器操作写入至多一个偶数字节范围和一个相邻的奇数字节范围。 第一偶数偏移识别由存储器存储器操作潜在地写入的第一偶数字节范围，并且第一奇数偏移识别潜在地由存储器存储器操作写入的第一奇数字节范围。 第一偶数掩模识别由存储器存储器操作写入的第一偶数字节范围内的字节，并且其中第一奇数掩码标识由存储器存储器操作写入的第一奇数字节范围内的字节。

公开(公告)号：US07721066B2

公开(公告)日：2010-05-18

申请号：US11758193

申请日：2007-06-05

申请人： Tse-yu Yeh ,  Daniel C. Murray ,  Po-Yung Chang ,  Anup S. Mehta

发明人： Tse-yu Yeh ,  Daniel C. Murray ,  Po-Yung Chang ,  Anup S. Mehta

IPC分类号： G06F12/00

CPC分类号： G06F12/0607

摘要： In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation. The first even mask identifies bytes within the first even byte range that are written by the store memory operation, and wherein the first odd mask identifies bytes within the first odd byte range that are written by the store memory operation.

摘要翻译： 在一个实施例中，装置包括包括多个条目的队列和耦合到队列的控制单元。 控制单元被配置为将第一队列条目分配给存储存储器操作，并且被配置为将对应于存储存储器操作的第一偶数偏移，第一偶数掩码，第一奇数偏移和第一奇数掩码写入到 第一次入场 一组连续的存储器位置在逻辑上被划分为交替寻址的偶数和奇数字节范围。 给定的存储器操作写入至多一个偶数字节范围和一个相邻的奇数字节范围。 第一偶数偏移识别由存储器存储器操作潜在地写入的第一偶数字节范围，并且第一奇数偏移识别潜在地由存储器存储器操作写入的第一奇数字节范围。 第一偶数掩模识别由存储器存储器操作写入的第一偶数字节范围内的字节，并且其中第一奇数掩码标识由存储器存储器操作写入的第一奇数字节范围内的字节。

公开(公告)号：US08553488B2

公开(公告)日：2013-10-08

申请号：US13157433

申请日：2011-06-10

申请人： Brian J. Campbell ,  Daniel C. Murray ,  Conrad H. Ziesler

发明人： Brian J. Campbell ,  Daniel C. Murray ,  Conrad H. Ziesler

IPC分类号： G11C5/14

CPC分类号： G11C29/04 ,  G11C8/08 ,  G11C29/30 ,  G11C2029/1202

摘要： A memory may include a memory array, a plurality of control circuits, and a plurality of isolation circuits. The plurality of control circuits may be configured to generate control signals for the memory array. For example, the plurality of control circuits may include a plurality of word line driver circuits. The plurality of isolation circuits may be configured to receive the control signals from the plurality of control circuits and a plurality of isolation signals. A first isolation signal may correspond to the plurality of word line driver circuits and at least one second isolation signal may correspond to other ones of the plurality of control circuits. The first isolation signal and the second isolation signal may be independently controlled during memory tests to detect stuck-at faults associated with the plurality of isolation signals.

摘要翻译： 存储器可以包括存储器阵列，多个控制电路和多个隔离电路。 多个控制电路可以被配置为产生用于存储器阵列的控制信号。 例如，多个控制电路可以包括多个字线驱动电路。 多个隔离电路可以被配置为从多个控制电路接收控制信号和多个隔离信号。 第一隔离信号可以对应于多个字线驱动器电路，并且至少一个第二隔离信号可以对应于多个控制电路中的其它控制电路。 可以在存储器测试期间独立地控制第一隔离信号和第二隔离信号，以检测与多个隔离信号相关联的卡入故障。

公开(公告)号：US07996662B2

公开(公告)日：2011-08-09

申请号：US11281832

申请日：2005-11-17

申请人： Wei-Han Lien ,  Daniel C. Murray ,  Junji Sugisawa

发明人： Wei-Han Lien ,  Daniel C. Murray ,  Junji Sugisawa

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/3842 ,  G06F9/30094 ,  G06F9/384 ,  G06F9/3863

摘要： In one embodiment, a processor comprises a plurality of storage locations, a decode circuit, and a status/control register (SCR). Each storage location is addressable as a speculative register and is configured to store result data generated during execution of an instruction operation and a value representing an update for the SCR. The value includes at least a first encoding that represents an update to a plurality of bits in the SCR, and a first number of bits in the plurality of bits is greater than a second number of bits in the first encoding. The decode circuit is coupled to receive the first encoding from a first storage location responsive to retirement of a first instruction operation assigned to use the first storage location as a destination, and is configured to decode the first encoding and generate the plurality of bits. The decode circuit is configured to update the SCR.

摘要翻译： 在一个实施例中，处理器包括多个存储位置，解码电路和状态/控制寄存器（SCR）。 每个存储位置可寻址为推测寄存器，并且被配置为存储在执行指令操作期间生成的结果数据和表示SCR的更新的值。 该值至少包括表示对SCR中的多个比特的更新的第一编码，并且多个比特中的第一比特数大于第一编码中的第二比特数。 解码电路被耦合以响应于分配给使用第一存储位置的目的地的第一指令操作的退出而从第一存储位置接收第一编码，并且被配置为对第一编码进行解码并生成多个位。 解码电路被配置为更新SCR。

公开(公告)号：US07996646B2

公开(公告)日：2011-08-09

申请号：US12721164

申请日：2010-03-10

申请人： Tse-yu Yeh ,  Daniel C. Murray ,  Po-Yung Chang ,  Anup S. Mehta

发明人： Tse-yu Yeh ,  Daniel C. Murray ,  Po-Yung Chang ,  Anup S. Mehta

IPC分类号： G06F12/00

CPC分类号： G06F12/0607

摘要： In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation. The first even mask identifies bytes within the first even byte range that are written by the store memory operation, and wherein the first odd mask identifies bytes within the first odd byte range that are written by the store memory operation.

摘要翻译： 在一个实施例中，装置包括包括多个条目的队列和耦合到队列的控制单元。 控制单元被配置为将第一队列条目分配给存储存储器操作，并且被配置为将对应于存储存储器操作的第一偶数偏移，第一偶数掩码，第一奇数偏移和第一奇数掩码写入到 第一次入场 一组连续的存储器位置在逻辑上被划分为交替寻址的偶数和奇数字节范围。 给定的存储器操作写入至多一个偶数字节范围和一个相邻的奇数字节范围。 第一偶数偏移识别由存储器存储器操作潜在地写入的第一偶数字节范围，并且第一奇数偏移识别潜在地由存储器存储器操作写入的第一奇数字节范围。 第一偶数掩模识别由存储器存储器操作写入的第一偶数字节范围内的字节，并且其中第一奇数掩码标识由存储器存储器操作写入的第一奇数字节范围内的字节。

公开(公告)号：US07355905B2

公开(公告)日：2008-04-08

申请号：US11173565

申请日：2005-07-01

申请人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

发明人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC分类号： G11C7/00

CPC分类号： G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

摘要： In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

摘要翻译： 在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。 即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。 在另一个实施例中，一种方法包括读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供有在使用期间大于所述第一电源电压的第二电源电压。

公开(公告)号：US07203827B2

公开(公告)日：2007-04-10

申请号：US11069771

申请日：2005-03-01

申请人： David A. Kruckemyer ,  Daniel C. Murray

发明人： David A. Kruckemyer ,  Daniel C. Murray

IPC分类号： G06F9/32

CPC分类号： G06F9/324 ,  G06F9/30054 ,  G06F9/3806

摘要： A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address of a first set of bytes including a branch instruction and a second address of a second set of bytes contiguous to the first set. The least significant bits of the branch PC (those bits not included in the most significant bits of the addresses received by the circuit) are used to generate the least significant bits of the link/sequential address and to select one of the first address and the second address to supply the most significant bits.

摘要翻译： 提供链路地址/顺序地址生成电路用于生成链路/顺序地址。 该电路接收至少两个地址的最高有效位：包括分支指令的第一组字节的第一地址和与第一组相邻的第二组字节的第二地址。 分支PC的最低有效位（不包括在由电路接收的地址的最高有效位中的位）被用于生成链路/顺序地址的最低有效位，并且选择第一地址和 第二个地址提供最重要的位。