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    All terrain vehicle
    2.
    发明授权
    All terrain vehicle 有权
    全地形车

    公开(公告)号：US08596398B2

    公开(公告)日：2013-12-03

    申请号：US12272377

    申请日：2008-11-17

    Applicant: Jeffrey David Bennett

    Inventor： Jeffrey David Bennett

    IPC: B62J25/00

    CPC classification number: F16D65/123 ,  B60G3/20 ,  B60G2200/144 ,  B60G2300/124 ,  B60K5/02 ,  B60K17/08 ,  B60K17/22 ,  B60T1/065 ,  B62J25/00 ,  B62K5/01 ,  B62K2005/001

    Abstract: The present disclosure relates to all-terrain vehicles (ATVs) having an ergonomically improved rider footwell and leg well. Specifically, the present disclosure relates to ATVs having an ergonomically designed footwell leg recess to allow the rider's leg to be received therein while standing.

    Abstract translation: 本公开涉及具有符合人体工程学改进的骑手脚部井和腿部井的全地形车辆（ATV）。 具体地，本公开涉及具有符合人体工程学设计的脚部空心腿部凹部的ATV，以允许骑车人的腿在站立时被容纳在其中。

    Mapping address table maintenance in a memory device
    5.
    发明授权
    Mapping address table maintenance in a memory device 有权
    映射存储设备中的地址表维护

    公开(公告)号：US08250333B2

    公开(公告)日：2012-08-21

    申请号：US12348782

    申请日：2009-01-05

    Applicant: Sergey Anatolievich Gorobets ,  Alexander Paley ,  Eugene Zilberman ,  Alan David Bennett ,  Shai Traister

    Inventor： Sergey Anatolievich Gorobets ,  Alexander Paley ,  Eugene Zilberman ,  Alan David Bennett ,  Shai Traister

    IPC: G06F12/12

    CPC classification number: G06F12/0246 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/7201 ,  G06F2212/7205

    Abstract: A method and system maintains an address table for mapping logical groups to physical addresses in a memory device. The method includes receiving a request to set an entry in the address table and selecting and flushing entries in an address table cache depending on the existence of the entry in the cache and whether the cache meets a flushing threshold criteria. The flushed entries include less than the maximum capacity of the address table cache. The flushing threshold criteria includes whether the address table cache is full or if a page exceeds a threshold of changed entries. The address table and/or the address table cache may be stored in a non-volatile memory and/or a random access memory. Improved performance may result using this method and system due to the reduced number of write operations and time needed to partially flush the address table cache to the address table.

    Abstract translation: 方法和系统维护用于将逻辑组映射到存储器设备中的物理地址的地址表。 该方法包括接收在地址表中设置条目的请求，并根据高速缓存中的条目的存在以及高速缓存是否满足冲洗阈值标准来选择和刷新地址表高速缓存中的条目。 刷新的条目包括小于地址表缓存的最大容量。 刷新阈值标准包括地址表缓存是否满或页面是否超过已更改条目的阈值。 地址表和/或地址表缓存可以存储在非易失性存储器和/或随机存取存储器中。 由于将地址表缓存部分刷新到地址表所需的写入操作次数和时间减少，因此可能会导致使用此方法和系统的性能提高。

    MODIFIED T CELL RECEPTORS AND RELATED MATERIALS AND METHODS
    7.
    发明申请
    MODIFIED T CELL RECEPTORS AND RELATED MATERIALS AND METHODS 有权
    改良的T细胞受体及相关材料与方法

    公开(公告)号：US20120071420A1

    公开(公告)日：2012-03-22

    申请号：US13304841

    申请日：2011-11-28

    Applicant: Paul F. Robbins ,  Richard A. Morgan ,  Steven A. Rosenberg ,  Alan David Bennett

    Inventor： Paul F. Robbins ,  Richard A. Morgan ,  Steven A. Rosenberg ,  Alan David Bennett

    IPC: A61K38/02 ,  A61P31/00 ,  C12Q1/02 ,  A61P35/00

    CPC classification number: G01N33/505 ,  A61K38/00 ,  C07K14/7051 ,  G01N33/5091

    Abstract: The invention is directed to a modified T cell receptor (TCR) comprising an amino acid sequence of a wild-type (WT) TCR with no more than three amino acid substitutions, wherein the modified TCR, as compared to the WT TCR, (i) has an enhanced ability to recognize target cells when expressed by CD4+ T cells and (ii) does not exhibit a decrease in antigen specificity when expressed by CD8+ T cells. Polypeptides, proteins, nucleic acids, recombinant expression vectors, host cells, populations of cells, antibodies, and pharmaceutical compositions related to the modified TCR also are part of the invention. Further, the invention is directed to methods of detecting a diseased cell in a host, methods of treating or preventing a disease in a host, and methods of identifying a candidate adoptive immunotherapy TCR.

    Abstract translation: 本发明涉及包含不超过三个氨基酸取代的野生型（WT）TCR的氨基酸序列的修饰的T细胞受体（TCR），其中与WT TCR相比，修饰的TCR（i ）当由CD4 + T细胞表达时具有增强的识别靶细胞的能力，和（ii）当由CD8 + T细胞表达时不显示抗原特异性的降低。 多肽，蛋白质，核酸，重组表达载体，宿主细胞，细胞群，抗体和与修饰的TCR相关的药物组合物也是本发明的一部分。 此外，本发明涉及检测宿主中的病变细胞的方法，治疗或预防宿主疾病的方法，以及鉴定候选的过继性免疫治疗TCR的方法。

    Adaptive deterministic grouping of blocks into multi-block units
    10.
    发明授权
    Adaptive deterministic grouping of blocks into multi-block units 有权
    块自适应确定性分组成多块单位

    公开(公告)号：US07970985B2

    公开(公告)日：2011-06-28

    申请号：US12512282

    申请日：2009-07-30

    Applicant: Carlos J. Gonzalez ,  Alan Douglas Bryce ,  Sergey Anatolievich Gorobets ,  Alan David Bennett

    Inventor： Carlos J. Gonzalez ,  Alan Douglas Bryce ,  Sergey Anatolievich Gorobets ,  Alan David Bennett

    IPC: G06F12/00

    CPC classification number: G11C29/76 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C29/808

    Abstract: The present invention presents techniques for the linking of physical blocks of a non-volatile memory into composite logical structures or “metablocks”. After determining an initial linking of good physical blocks into metablocks, a record of the linking is maintained in the non-volatile memory where it can be readily accessed when needed. In one set of embodiments, the initially linking is deterministically formed according to an algorithm and can be optimized according to the pattern of any bad blocks in the memory. As additional bad blocks arise, the linking is updated using by replacing the bad blocks in a linking with good blocks, preferably in the same sub-array of the memory as the block that they are replacing.

    Abstract translation: 本发明提出了用于将非易失性存储器的物理块链接到复合逻辑结构或“元区块”中的技术。 在确定好的物理块到元区块的初始链接之后，在非易失性存储器中维护链接的记录，在需要时可以容易地访问。 在一组实施例中，根据算法确定性地形成初始链接，并且可以根据存储器中的任何坏块的模式进行优化。 随着额外的坏块出现，链接被更新，通过替换与优质块链接的坏块，优选地与它们所替换的块相同的存储器子阵列来更新。

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