公开(公告)号：US06590817B2

公开(公告)日：2003-07-08

申请号：US09912245

申请日：2001-07-23

申请人： David D. Siek

发明人： David D. Siek

IPC分类号： G11C700

CPC分类号： G11C29/50 ,  G11C11/401 ,  G11C11/404 ,  G11C29/32 ,  G11C2029/0403 ,  H01L27/0207 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10873 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897

摘要： The present invention includes a 6F2 DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and second memory cells. The isolation gate is configured to provide electrical isolation between the first and second memory cells. The DRAM also includes a first switch having first and second load electrodes and a control electrode configured to accept a first control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to ground. The DRAM additionally includes a second switch having first and second load electrodes and a control electrode configured to accept a second control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to a stress voltage source.

摘要翻译： 本发明包括6F2 DRAM阵列。 DRAM阵列包括形成在第一和第二存储单元之间的第一存储单元，第二存储单元和隔离栅。 隔离栅极被配置为在第一和第二存储器单元之间提供电隔离。 DRAM还包括具有第一和第二负载电极的第一开关和被配置为接受第一控制信号的控制电极。 第一负载电极耦合到隔离栅极，第二负载电极耦合到地。 DRAM还包括具有第一和第二负载电极的第二开关和被配置为接受第二控制信号的控制电极。 第一负载电极耦合到隔离栅极，第二负载电极耦合到应力电压源。

公开(公告)号：US07180802B2

公开(公告)日：2007-02-20

申请号：US11171872

申请日：2005-06-30

申请人： David D. Siek

发明人： David D. Siek

IPC分类号： G11C7/00

CPC分类号： G11C29/50 ,  G11C11/401 ,  G11C11/404 ,  G11C29/32 ,  G11C2029/0403 ,  H01L27/0207 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10873 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897

摘要： The present invention includes a DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and second memory cells. The isolation gate is configured to provide electrical isolation between the first and second memory cells. The DRAM also includes a first switch having first and second load electrodes and a control electrode configured to accept a first control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to ground. The DRAM additionally includes a second switch having first and second load electrodes and a control electrode configured to accept a second control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to a stress voltage source.

摘要翻译： 本发明包括DRAM阵列。 DRAM阵列包括形成在第一和第二存储单元之间的第一存储单元，第二存储单元和隔离栅。 隔离栅极被配置为在第一和第二存储器单元之间提供电隔离。 DRAM还包括具有第一和第二负载电极的第一开关和被配置为接受第一控制信号的控制电极。 第一负载电极耦合到隔离栅极，第二负载电极耦合到地。 DRAM还包括具有第一和第二负载电极的第二开关和被配置为接受第二控制信号的控制电极。 第一负载电极耦合到隔离栅极，第二负载电极耦合到应力电压源。

公开(公告)号：US06930503B2

公开(公告)日：2005-08-16

申请号：US10835945

申请日：2004-04-30

申请人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

发明人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

IPC分类号： G01R31/26 ,  G01R31/30 ,  G11C5/14 ,  G11C29/02 ,  G11C29/12 ,  G01R31/02 ,  G11C29/00

CPC分类号： G11C29/02 ,  G01R31/3004 ,  G11C5/145 ,  G11C5/146 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C2029/5004

摘要： A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

摘要翻译： 用于产生用于封装的集成电路存储器件的内部电压的电压产生电路是可控的，以提供用于存储器件测试的电压的增量调节。 电压产生电路允许存储器件的内部产生的电压，例如衬底电压Vbb，DVC2电压和泵浦电压Vccp，通过经由常规测试功能施加测试信号在外部进行控制，以执行标准器件 诸如静态刷新测试，逻辑1s和0s裕量测试之类的测试，等等用于封装的存储器件。 此外，提供了包括可编程逻辑器件（例如抗熔丝）的可编程电路，其可编程以将电压维持在其调节幅度。

公开(公告)号：US06510533B1

公开(公告)日：2003-01-21

申请号：US09749854

申请日：2000-12-26

申请人： David D. Siek ,  Tim G. Damon

发明人： David D. Siek ,  Tim G. Damon

IPC分类号： G11C2900

CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C29/26 ,  G11C29/50

摘要： A method of testing and/or repairing a memory device having two arrays of memory cells arranged in rows and columns. Sense amplifiers shared by the arrays are selectively coupled by isolation transistors to the digit lines of respective columns in each array. The sense amplifiers and isolation transistors are controlled to sequentially writing known data bits to a plurality of rows in each of the arrays. The rows in the first and second arrays remain activated for a testing interval of sufficient duration to allow charge to transfer through any inter-cell defects between the cells in the activated rows and cells that are not in an activated row. Cells in each non-activated row are then read. Inter-cell defects may also be repaired by activating the rows in the first and second arrays in a manner that couples adjacent memory cells to digit lines having different complimentary voltages.

摘要翻译： 一种测试和/或修复具有以行和列排列的两组存储单元的存储器件的方法。 由阵列共享的感测放大器通过隔离晶体管选择性地耦合到每个阵列中各列的数字线。 控制读出放大器和隔离晶体管以将已知数据位顺序地写入每个阵列中的多行。 第一和第二阵列中的行保持激活持续时间的测试间隔，以允许电荷通过激活的行中的单元之间的任何单元间缺陷和不在激活行中的单元传送。 然后读取每个未激活行中的单元格。 也可以通过以相互相邻的存储单元耦合到具有不同互补电压的数字线的方式激活第一和第二阵列中的行来修复单元间缺陷。

公开(公告)号：US06496027B1

公开(公告)日：2002-12-17

申请号：US08916994

申请日：1997-08-21

申请人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

发明人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

IPC分类号： G01R3102

CPC分类号： G11C29/02 ,  G01R31/3004 ,  G11C5/145 ,  G11C5/146 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C2029/5004

摘要： A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

摘要翻译： 用于产生用于封装的集成电路存储器件的内部电压的电压产生电路是可控的，以提供用于存储器件测试的电压的增量调节。 电压产生电路允许存储器件的内部产生的电压，例如衬底电压Vbb，DVC2电压和泵浦电压Vccp，通过经由常规测试功能施加测试信号在外部进行控制，以执行标准器件 诸如静态刷新测试，逻辑1s和0s裕量测试之类的测试，等等用于封装的存储器件。 此外，提供了包括可编程逻辑器件（例如抗熔丝）的可编程电路，其可编程以将电压维持在其调节幅度。

公开(公告)号：US6167541A

公开(公告)日：2000-12-26

申请号：US47760

申请日：1998-03-24

申请人： David D. Siek ,  Tim G. Damon

发明人： David D. Siek ,  Tim G. Damon

IPC分类号： G11C29/02 ,  G11C29/26 ,  G11C29/50 ,  G11C29/00

CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C29/26 ,  G11C29/50

摘要： A method of testing a memory device having two arrays of memory cells arranged in rows and columns. Sense amplifiers for respective columns are shared by the arrays, with the sense amplifiers being selectively coupled to the digit lines of respective columns in each array by respective isolation transistors. Cells of the memory array are tested by first writing known data bits to each of the cells. The isolation transistors for the first array are then turned on, and the isolation transistors for the second array are turned off. Predetermined voltages are coupled to the sense amplifiers through the digit lines of the first array by activating a row in the first array. A plurality of rows in the first array are then activated to couple the memory cells in each activated row to respective digit lines. The sense amplifiers are then coupled to respective digit lines in the second array by turning on the isolation transistors for the second array. A plurality of rows in the second array are then activated to couple the memory cells in each activated row to respective digit lines of the second array. The rows in the first and second arrays remain activated for a testing interval of sufficient duration to allow charge to transfer through any inter-cell defects between the cells in the activated rows and cells that are not in an activated row. The cells that are not in an activated row are then read to determine if the data originally written to the cells was altered by charge flowing through inter-cell defects. Inter-cell defects may also be repaired by activating the rows in the first and second arrays in a manner that couples adjacent memory cells to digit lines having different complimentary voltages.

摘要翻译： 一种测试具有以行和列排列的两组存储单元的存储器件的方法。 用于各列的感测放大器由阵列共享，读出放大器通过相应的隔离晶体管选择性地耦合到每个阵列中各列的数字线。 通过首先将已知数据位写入每个单元来测试存储器阵列的单元。 然后，第一阵列的隔离晶体管导通，并且用于第二阵列的隔离晶体管截止。 通过激活第一阵列中的一行，预定电压通过第一阵列的数字线耦合到读出放大器。 然后激活第一阵列中的多个行以将每个激活的行中的存储单元耦合到相应的数字行。 然后，通过接通第二阵列的隔离晶体管，将读出放大器耦合到第二阵列中的各个数字线。 然后激活第二阵列中的多行以将每个激活的行中的存储单元耦合到第二阵列的相应数字线。 第一和第二阵列中的行保持激活持续时间的测试间隔，以允许电荷通过激活的行中的单元之间的任何单元间缺陷和不在激活行中的单元传输。 然后读取不在激活行中的单元，以确定原始写入单元的数据是否由流经单元间缺陷的电荷而改变。 也可以通过以相互相邻的存储单元耦合到具有不同互补电压的数字线的方式激活第一和第二阵列中的行来修复单元间缺陷。

公开(公告)号：US6066870A

公开(公告)日：2000-05-23

申请号：US109458

申请日：1998-07-02

申请人： David D. Siek

发明人： David D. Siek

IPC分类号： G11C7/12 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10808 ,  G11C11/4091 ,  G11C11/4097 ,  G11C7/12 ,  H01L27/10805 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/907

摘要： An integrated memory circuit comprises a plurality of memory cells and access transistors; and a digit line comprising conductive tabs extending from at least one side of a conductive digit line. The use of one digit line allows for a reduction in internal noise and coupling between digit line pairs. The use of one digit line also allows for a reduction in array size.

摘要翻译： 集成存储电路包括多个存储单元和存取晶体管; 以及数字线，包括从导电数字线的至少一侧延伸的导电片。 使用一位数字线可以减少内部噪声和数字线对之间的耦合。 使用一位数字线也可以减少阵列大小。

公开(公告)号：US5986955A

公开(公告)日：1999-11-16

申请号：US234268

申请日：1999-01-19

申请人： David D. Siek ,  Rajesh Somasekharan

发明人： David D. Siek ,  Rajesh Somasekharan

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1006

摘要： A hidden data path minimizes equilibration delays in coupling differential data through a complementary data path. The hidden data path may be used for both reading and writing to the memory cell array. The hidden data path includes two sets of complementary I/O lines coupled in parallel between the memory cell array and the DC sense amplifier, and are alternatively coupled between the memory cell array and the DC sense amplifier to receive and transmit data. The set of complementary I/O lines not coupled is equilibrated during this time in preparation for coupling to and transmitting subsequent differential data. The hidden data path may also include two sets of data read lines coupled in parallel between the DC sense amplifier and the output circuitry if used for reading data from the memory cell array. Similarly, a second set of data write lines may be coupled in parallel between the input circuitry and write driver circuit when used for writing data to the memory cell array.

摘要翻译： 隐藏的数据路径通过补充数据路径使差分数据的平衡延迟最小化。 隐藏的数据路径可以用于读取和写入存储器单元阵列。 隐藏数据路径包括并联在存储单元阵列和DC读出放大器之间的两组互补I / O线，并且交替耦合在存储单元阵列和DC读出放大器之间以接收和发送数据。 在此期间，不耦合的互补I / O线的平衡被准备用于耦合到并传送随后的差分数据。 如果用于从存储单元阵列读取数据，隐藏数据路径还可以包括并联在DC读出放大器和输出电路之间的两组数据读取线。 类似地，当用于将数据写入存储单元阵列时，第二组数据写入线可以并联连接在输入电路和写入驱动器电路之间。

公开(公告)号：US06735132B2

公开(公告)日：2004-05-11

申请号：US10439729

申请日：2003-05-16

申请人： David D. Siek

发明人： David D. Siek

IPC分类号： G11C700

CPC分类号： G11C29/50 ,  G11C11/401 ,  G11C11/404 ,  G11C29/32 ,  G11C2029/0403 ,  H01L27/0207 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10873 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897

摘要： The present invention includes a 6F2 DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and second memory cells. The isolation gate is configured to provide electrical isolation between the first and second memory cells. The DRAM also includes a first switch having first and second load electrodes and a control electrode configured to accept a first control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to ground. The DRAM additionally includes a second switch having first and second load electrodes and a control electrode configured to accept a second control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to a stress voltage source.

摘要翻译： 本发明包括6F 2 DRAM阵列。 DRAM阵列包括形成在第一和第二存储单元之间的第一存储单元，第二存储单元和隔离栅。 隔离栅极被配置为在第一和第二存储器单元之间提供电隔离。 DRAM还包括具有第一和第二负载电极的第一开关和被配置为接受第一控制信号的控制电极。 第一负载电极耦合到隔离栅极，第二负载电极耦合到地。 DRAM还包括具有第一和第二负载电极的第二开关和被配置为接受第二控制信号的控制电极。 第一负载电极耦合到隔离栅极，第二负载电极耦合到应力电压源。

公开(公告)号：US5866928A

公开(公告)日：1999-02-02

申请号：US671315

申请日：1996-07-16

申请人： David D. Siek

发明人： David D. Siek

IPC分类号： G11C7/12 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10808 ,  G11C11/4091 ,  G11C11/4097 ,  G11C7/12 ,  H01L27/10805 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/907

摘要： An integrated memory circuit comprises a plurality of memory cells and access transistors; and a digit line comprising conductive tabs extending from at least one side of a conductive digit line. The use of one digit line allows for a reduction in internal noise and coupling between digit line pairs. The use of one digit line also allows for a reduction in array size.