Method and apparatus to interface semiconductor storage device and host to provide performance throttling of semiconductor storage device
    1.
    发明授权
    Method and apparatus to interface semiconductor storage device and host to provide performance throttling of semiconductor storage device 有权
    接口半导体存储设备和主机以提供半导体存储设备的性能调节的方法和设备

    公开(公告)号:US09037778B2

    公开(公告)日:2015-05-19

    申请号:US13212404

    申请日:2011-08-18

    IPC分类号: G06F12/00 G06F3/06

    摘要: A method and apparatus to interface a semiconductor storage device and a host in order to provide performance throttling of the semiconductor storage device. In the method, the semiconductor storage can receive a setting request command from the host. The semiconductor storage device sets a performance throttling parameter to a particular value in response to the setting request command. The semiconductor storage device can send to the host a setting response signal indicating completion of the setting of the performance throttling parameter.

    摘要翻译: 一种用于将半导体存储设备和主机接口以便提供半导体存储设备的性能调节的方法和设备。 在该方法中,半导体存储器可以从主机接收设置请求命令。 半导体存储装置响应于设置请求命令将性能调节参数设置为特定值。 半导体存储装置可以向主机发送指示性能调节参数的设置的完成的设置响应信号。

    Non-volatile memory device, operation method thereof, and devices having the non-volatile memory device
    9.
    发明授权
    Non-volatile memory device, operation method thereof, and devices having the non-volatile memory device 有权
    非易失性存储器件,其操作方法以及具有非易失性存储器件的器件

    公开(公告)号:US08508990B2

    公开(公告)日:2013-08-13

    申请号:US13071727

    申请日:2011-03-25

    IPC分类号: G11C16/04

    CPC分类号: G11C11/5628 G11C16/3454

    摘要: A non-volatile memory device includes a memory cell array including a plurality of multi-level cells each storing data corresponding to one of a plurality of states of a first group of states, and a control circuit. The control circuit is configured to program data corresponding to one of the plurality of states in a first multi-level cell according to a first verify voltage level of a first group of verify voltage levels, and to control the first multi-level cell to be re-programmed to one of a plurality of states of a second group of states according to a first verify voltage level of a second group of verify voltage levels. Each voltage level of the second group of verify voltage levels has a higher level than the verify voltage levels of the first group of verify voltage levels.

    摘要翻译: 非易失性存储器件包括存储单元阵列,该存储单元阵列包括多个多电平单元,每个多电平单元存储对应于第一组状态的多种状态之一的数据,以及控制电路。 控制电路被配置为根据第一组验证电压电平的第一验证电压电平对与第一多电平单元中的多个状态中的一个状态相对应的数据,并且将第一多电平单元控制为 根据第二组验证电压电平的第一验证电压电平,将其重新编程为第二组状态的多个状态之一。 第二组验证电压电平的每个电压电平具有比第一组验证电压电平的验证电压电平更高的电平。

    METHOD AND APPARATUS TO INTERFACE SEMICONDUCTOR STORAGE DEVICE AND HOST TO PROVIDE PERFORMANCE THROTTLING OF SEMICONDUCTOR STORAGE DEVICE
    10.
    发明申请
    METHOD AND APPARATUS TO INTERFACE SEMICONDUCTOR STORAGE DEVICE AND HOST TO PROVIDE PERFORMANCE THROTTLING OF SEMICONDUCTOR STORAGE DEVICE 有权
    用于界面半导体存储器件的方法和装置和主机提供半导体存储器件的性能曲线

    公开(公告)号:US20120047320A1

    公开(公告)日:2012-02-23

    申请号:US13212404

    申请日:2011-08-18

    IPC分类号: G06F12/02

    摘要: A method and apparatus to interface a semiconductor storage device and a host in order to provide performance throttling of the semiconductor storage device. In the method, the semiconductor storage can receive a setting request command from the host. The semiconductor storage device sets a performance throttling parameter to a particular value in response to the setting request command. The semiconductor storage device can send to the host a setting response signal indicating completion of the setting of the performance throttling parameter.

    摘要翻译: 一种用于将半导体存储设备和主机接口以便提供半导体存储设备的性能调节的方法和设备。 在该方法中,半导体存储器可以从主机接收设置请求命令。 半导体存储装置响应于设置请求命令将性能调节参数设置为特定值。 半导体存储装置可以向主机发送指示性能调节参数的设置的完成的设置响应信号。