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1.发明授权Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers 有权通过改变应力介电覆盖层的去除速率，在替代浇口方法中暴露占位符材料的技术公开(公告)号：US08247281B2
公开(公告)日：2012-08-21
申请号：US12822789
申请日：2010-06-24
IPC分类号： H01L21/8238
CPC分类号： H01L21/823425 , H01L21/31055 , H01L21/31111 , H01L21/76825 , H01L21/76829 , H01L21/7684 , H01L21/823412 , H01L21/823807 , H01L29/7843
摘要： In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.
摘要翻译： 在替代栅极方法中，通过例如在湿化学蚀刻步骤或CMP工艺期间，基于增强的工艺均匀性来暴露牺牲栅极材料，通过通过离子注入在层间绝缘材料中形成改性部分。 因此，当应用CMP工艺时，在施加蚀刻工艺或避免过度抛光时间的同时，可以以更高的去除速率去除损坏的部分，同时避免产生聚合物污染物。
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2.发明授权Method of forming CMOS device having gate insulation layers of different type and thickness 有权形成具有不同类型和厚度的栅极绝缘层的CMOS器件的方法公开(公告)号：US08021942B2
公开(公告)日：2011-09-20
申请号：US12049548
申请日：2008-03-17
申请人： Andy Wei , Andrew Waite , Martin Trentzsch , Johannes Groschopf , Gunter Grasshoff , Andreas Ott
发明人： Andy Wei , Andrew Waite , Martin Trentzsch , Johannes Groschopf , Gunter Grasshoff , Andreas Ott
IPC分类号： H01L21/8238 , H01L21/70 , H01L27/092
CPC分类号： H01L21/82345 , H01L21/823462 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/84 , H01L27/088 , H01L27/0922 , H01L29/66545 , H01L29/7843 , H01L29/7848 , Y10S438/926
摘要： In the process sequence for replacing conventional gate electrode structures by high-k metal gate structures, the number of additional masking steps may be maintained at a low level, for instance by using highly selective etch steps, thereby maintaining a high degree of compatibility with conventional CMOS techniques. Furthermore, the techniques disclosed herein enable compatibility to front-end process techniques and back-end process techniques, thereby allowing the integration of well-established strain-inducing mechanisms in the transistor level as well as in the contact level.
摘要翻译： 在通过高k金属栅极结构代替常规栅电极结构的工艺顺序中，例如通过使用高选择性蚀刻步骤，附加掩模步骤的数量可以保持在低水平，从而保持与常规栅极结构的高度兼容性 CMOS技术。 此外，本文公开的技术使得能够与前端处理技术和后端处理技术兼容，从而允许将已建立的应变诱发机制集成在晶体管级以及接触级中。
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3.发明授权Forming semiconductor resistors in a semiconductor device comprising metal gates by increasing etch resistivity of the resistors 有权通过增加电阻器的蚀刻电阻率，在包括金属栅极的半导体器件中形成半导体电阻器公开(公告)号：US08338306B2
公开(公告)日：2012-12-25
申请号：US12886765
申请日：2010-09-21
申请人： Jens Heinrich , Ralf Richter , Katja Steffen , Johannes Groschopf , Frank Seliger , Andreas Ott , Manfred Heinz , Andy Wei
发明人： Jens Heinrich , Ralf Richter , Katja Steffen , Johannes Groschopf , Frank Seliger , Andreas Ott , Manfred Heinz , Andy Wei
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L27/0629
摘要： In a replacement gate approach, the polysilicon material may be efficiently removed during a wet chemical etch process, while the semiconductor material in the resistive structures may be substantially preserved. For this purpose, a species such as xenon may be incorporated into the semiconductor material of the resistive structure, thereby imparting a significantly increased etch resistivity to the semiconductor material. The xenon may be incorporated at any appropriate manufacturing stage.
摘要翻译： 在替代栅极方法中，可以在湿化学蚀刻工艺期间有效地去除多晶硅材料，同时电阻结构中的半导体材料可以被基本保持。 为此，可以将诸如氙的物质并入电阻结构的半导体材料中，从而赋予半导体材料显着增加的蚀刻电阻率。 氙气可以在任何适当的生产阶段进行。
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4.发明申请TECHNIQUE FOR EXPOSING A PLACEHOLDER MATERIAL IN A REPLACEMENT GATE APPROACH BY MODIFYING A REMOVAL RATE OF STRESSED DIELECTRIC OVERLAYERS 有权通过修改压电介质覆盖层的去除速率来更换替代门方法中的位置材料的技术公开(公告)号：US20120282764A1
公开(公告)日：2012-11-08
申请号：US13550435
申请日：2012-07-16
IPC分类号： H01L21/283 , H01L21/302
CPC分类号： H01L21/823425 , H01L21/31055 , H01L21/31111 , H01L21/76825 , H01L21/76829 , H01L21/7684 , H01L21/823412 , H01L21/823807 , H01L29/7843
摘要： In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.
摘要翻译： 在替代栅极方法中，通过例如在湿化学蚀刻步骤或CMP工艺期间，基于增强的工艺均匀性来暴露牺牲栅极材料，通过通过离子注入在层间绝缘材料中形成改性部分。 因此，当应用CMP工艺时，在施加蚀刻工艺或避免过度抛光时间的同时，可以以更高的去除速率去除损坏的部分，同时避免产生聚合物污染物。
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5.发明授权Method for reducing polish-induced damage in a contact structure by forming a capping layer 失效通过形成覆盖层来减少接触结构中抛光引起的损伤的方法公开(公告)号：US07528059B2
公开(公告)日：2009-05-05
申请号：US11559652
申请日：2006-11-14
申请人： Kai Frohberg , Sandra Bau , Johannes Groschopf
发明人： Kai Frohberg , Sandra Bau , Johannes Groschopf
IPC分类号： H01L21/00
CPC分类号： H01L21/76801 , H01L21/76819 , H01L21/76829 , H01L21/7684
摘要： By forming a capping layer after a CMP process for planarizing the surface topography of an ILD layer, any surface irregularities may be efficiently sealed, thereby reducing the risk for forming conductive surface irregularities during the further processing. Consequently, yield loss effects caused by leakage paths or short circuits in the first metallization layer may be significantly reduced.
摘要翻译： 通过在用于平坦化ILD层的表面形貌的CMP工艺之后形成覆盖层，可以有效地密封任何表面凹凸，从而降低在进一步处理期间形成导电表面不规则性的风险。 因此，可以显着地减少由第一金属化层中的泄漏路径或短路引起的屈服损失效应。
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6.发明申请公开(公告)号：US20080090368A1
公开(公告)日：2008-04-17
申请号：US11580952
申请日：2006-10-16
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L21/31144 , H01L29/66659 , H01L29/66772
摘要： Methods are provided for the fabrication of abrupt and tunable offset spacers for improved transistor short channel control. The methods include the formation of a gate electrode within a dielectric layer, with only a top portion of the gate electrode exposed. Silicon is added on the top portion of the gate electrode, by selective epitaxial growth, for example. Etching of the dielectric layer is performed with added silicon at the top portion of the gate electrode serving as a silicon mask to prevent etching of the dielectric layer directly underneath the silicon mask, which includes overhangs over the gate electrode sidewalls. The etching creates offset spacers in a production-worthy manner, and can be used to form offset spacers that are asymmetrical in width. By running the methodology in a microloading regime, wider offset spacers may be created on narrower polysilicon gate features, thereby improving Vt roll-off.
摘要翻译： 提供了用于制造用于改善晶体管短沟道控制的突发和可调偏移间隔物的方法。 这些方法包括在电介质层内形成栅电极，仅露出栅电极的顶部。 例如，通过选择性外延生长将硅添加到栅电极的顶部。 介电层的蚀刻是在栅电极的顶部添加硅作为硅掩模进行的，以防止直接在硅掩模下面的电介质层的蚀刻，该掩模包括在栅电极侧壁上的突出端。 蚀刻以生产价值的方式产生偏移间隔物，并且可以用于形成不对称宽度的偏移间隔物。 通过在微加载方案中运行该方法，可以在较窄的多晶硅栅极特征上产生更宽的偏移间隔物，从而改善Vt滚降。
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7.发明申请Trench replacement gate process for transistors having elevated source and drain regions 审中-公开具有升高的源极和漏极区域的晶体管的沟槽替换栅极工艺公开(公告)号：US20080070356A1
公开(公告)日：2008-03-20
申请号：US11520607
申请日：2006-09-14
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/41783 , H01L21/28114 , H01L21/823814 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/66606
摘要： The method for forming a semiconductor device arrangement with raised source/drains includes depositing a raised source/drain layer on a substrate, followed by a sacrificial layer on the raised source/drain layer. A trench is formed in the sacrificial layer and the raised source/drain layer, and sidewall spacers are formed within the trench. A replacement gate is formed between the sidewall spacers and the sacrificial layer is removed to expose the raised source/drain regions. The sidewall spacers may then be removed from the sidewalls of the replacement gate, leaving the replacement gate a defined distance from the raised source/drain regions.
摘要翻译： 用于形成具有升高的源极/漏极的半导体器件布置的方法包括在衬底上沉积凸起的源极/漏极层，随后在凸起的源极/漏极层上沉积牺牲层。 在牺牲层和凸起的源极/漏极层中形成沟槽，并且在沟槽内形成侧壁间隔物。 在侧壁间隔件之间形成替换栅极，去除牺牲层以露出升高的源极/漏极区域。 然后可以从替换浇口的侧壁去除侧壁间隔物，使替换浇口与凸起的源极/漏极区域保持一定距离。
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8.发明申请Method of reducing STI divot formation during semiconductor device fabrication 有权在半导体器件制造期间减少STI纹路形成的方法公开(公告)号：US20050196928A1
公开(公告)日：2005-09-08
申请号：US10791759
申请日：2004-03-04
申请人： Douglas Bonser , Johannes Groschopf , Srikanteswara Dakshina-Murthy , John Pellerin , Jon Cheek
发明人： Douglas Bonser , Johannes Groschopf , Srikanteswara Dakshina-Murthy , John Pellerin , Jon Cheek
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/336
CPC分类号： H01L21/76224
摘要： STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer, e.g., no thicker than 400 Å. The very thin nitride polish stop layer is retained in place during subsequent masking, implanting and cleaning steps to form dopant regions, and is removed prior to gate oxide and gate electrode formation.
摘要翻译： 通过使用非常薄的氮化物抛光停止层例如不厚于400来消除或显着降低STI纹线形成。 非常薄的氮化物抛光停止层在随后的掩模，注入和清洁步骤中保持就位以形成掺杂剂区域，并且在栅极氧化物和栅电极形成之前被去除。
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9.发明授权Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers 有权通过改变应力介电覆盖层的去除速率，在替代浇口方法中暴露占位符材料的技术公开(公告)号：US08357575B2
公开(公告)日：2013-01-22
申请号：US13550435
申请日：2012-07-16
IPC分类号： H01L21/8238
CPC分类号： H01L21/823425 , H01L21/31055 , H01L21/31111 , H01L21/76825 , H01L21/76829 , H01L21/7684 , H01L21/823412 , H01L21/823807 , H01L29/7843
摘要： In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.
摘要翻译： 在替代栅极方法中，通过例如在湿化学蚀刻步骤或CMP工艺期间，基于增强的工艺均匀性来暴露牺牲栅极材料，通过通过离子注入在层间绝缘材料中形成改性部分。 因此，当应用CMP工艺时，在施加蚀刻工艺或避免过度抛光时间的同时，可以以更高的去除速率去除损坏的部分，同时避免产生聚合物污染物。
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10.发明申请Planarization of a Material System in a Semiconductor Device by Using a Non-Selective In Situ Prepared Slurry 有权通过使用非选择性原位制备的浆料对半导体器件中的材料系统进行平面化公开(公告)号：US20110269381A1
公开(公告)日：2011-11-03
申请号：US12969969
申请日：2010-12-16
IPC分类号： B24B1/00
CPC分类号： H01L21/31053 , H01L29/66545 , H01L29/7833
摘要： For complex CMP processes requiring the removal of different dielectric materials, possibly in the presence of a polysilicon material, a slurry material may be adapted at the point of use by selecting an appropriate pH value and avoiding agglomeration of the abrasive particles. The in situ preparation of the slurry material may also enable a highly dynamic adaptation of the removal conditions, for instance when exposing the polysilicon material of gate electrode structures in replacement gate approaches.
摘要翻译： 对于需要去除不同介电材料（可能存在多晶硅材料）的复杂CMP工艺，可以通过选择适当的pH值并避免磨料颗粒的团聚，在使用时适应浆料。 泥浆材料的原位制备还可以实现去除条件的高度动态适应，例如当在替代浇口方法中暴露栅电极结构的多晶硅材料时。
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