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    ANTENNA TUNER AND METHOD FOR ADJUSTING ANTENNA IMPEDANCE
    1.
    发明申请
    ANTENNA TUNER AND METHOD FOR ADJUSTING ANTENNA IMPEDANCE 失效
    天线调谐器和调整天线阻抗的方法

    公开(公告)号：US20130135060A1

    公开(公告)日：2013-05-30

    申请号：US13326037

    申请日：2011-12-14

    申请人： Jongsoo LEE ,  Ki Chul Kim

    发明人： Jongsoo LEE ,  Ki Chul Kim

    IPC分类号： H03H7/38

    CPC分类号： H03H7/40 ,  H04B1/0458

    摘要： Disclosed are an antenna tuner and a method for adjusting antenna impedance. The antenna tuner includes a reference impedance resistor, a first coupler having an isolated port connected to one end of the reference impedance resistor, a second coupler having an input port connected to an output port of the first coupler and an output port connected to the antenna, and an impedance adjusting device group connected to the second coupler to adjust impedance of the antenna. An impedance controller generates an impedance adjustment control signal according to a first voltage applied to a coupled port of the first coupler, and a second voltage applied to a coupled port of the second coupler to provide the impedance adjustment control signal to the impedance adjusting device group.

    摘要翻译： 公开了天线调谐器和调整天线阻抗的方法。 天线调谐器包括参考阻抗电阻器，具有连接到参考阻抗电阻器一端的隔离端口的第一耦合器，具有连接到第一耦合器的输出端口的输入端口的第二耦合器和连接到天线的输出端口 以及连接到第二耦合器以调整天线的阻抗的阻抗调节装置组。 阻抗控制器根据施加到第一耦合器的耦合端口的第一电压和施加到第二耦合器的耦合端口的第二电压产生阻抗调整控制信号，以向阻抗调节装置组提供阻抗调节控制信号 。

    VALVE CONTROL SYSTEM, BIDET USING THE SAME, AND VALVE CONTROL METHOD
    2.
    发明申请
    VALVE CONTROL SYSTEM, BIDET USING THE SAME, AND VALVE CONTROL METHOD 有权
    阀门控制系统，使用该阀门的阀门和阀门控制方法

    公开(公告)号：US20130091628A1

    公开(公告)日：2013-04-18

    申请号：US13805947

    申请日：2011-06-29

    申请人： Joung-Ho Son ,  In-Seok Seo ,  Ki-Chul Kim

    发明人： Joung-Ho Son ,  In-Seok Seo ,  Ki-Chul Kim

    IPC分类号： E03D9/08 ,  F16K17/20

    CPC分类号： E03D9/08 ,  E03B7/071 ,  F16K17/20 ,  F16K37/0091 ,  Y10T137/0324 ,  Y10T137/7722

    摘要： There are provided a valve control system, a bidet using the same, and a valve control method. The valve control system includes a latch valve controlling a stream of water in a pipe; a flow rate sensor measuring a flow rate in the pipe; and a valve control device controlling the operation of the latch valve. The valve control device determines whether or not the latch valve is malfunctioning upon analyzing a flow rate measured by the flow rate sensor. When the latch valve is malfunctioning, the valve control device controls the latch valve to re-operate.

    摘要翻译： 提供了阀控制系统，使用其的坐浴盆和阀控制方法。 阀控制系统包括控制管道中的水流的闭锁阀; 测量管道中的流量的流量传感器; 以及控制所述闩锁阀的操作的阀控制装置。 阀控制装置在分析由流量传感器测量的流量时，判定是否有闩锁阀故障。 当闩锁阀故障时，阀门控制装置控制闩锁阀重新操作。

    VALVE EXHAUSTING APPARATUS AND A DRIER OF FOOD TREATMENT SYSTEM HAVING IT
    4.
    发明申请
    VALVE EXHAUSTING APPARATUS AND A DRIER OF FOOD TREATMENT SYSTEM HAVING IT 审中-公开
    阀门排料装置和食品处理系统的干燥器

    公开(公告)号：US20110078915A1

    公开(公告)日：2011-04-07

    申请号：US12921139

    申请日：2008-09-04

    申请人： Sung Jin Kim ,  Sang Gu Sim ,  Ki Chul Kim

    发明人： Sung Jin Kim ,  Sang Gu Sim ,  Ki Chul Kim

    IPC分类号： D06F58/04 ,  B02C7/12 ,  F16K31/04

    CPC分类号： A23L3/40 ,  F26B11/16 ,  F26B25/002

    摘要： An exhaust valve apparatus and a drier of a food treatment system having the exhaust valve apparatus are disclosed. The drier includes a drum having an input port and a discharge port. A stirring screw is rotatably disposed in the drum, and includes rotary blades for stirring and crushing the food waste and a rotating shaft for supporting the rotary blades. A power supply unit is provided on a surface of the drum and provides power to the stirring screw to rotate the stirring screw. A heater is provided on the outer surface of the drum body and provides high temperature heat to the inner space of the drum when electric power is applied to the heater, thus drying the food waste. An exhaust apparatus is mounted to the lower surface of the discharge port to open or close the discharge port.

    摘要翻译： 公开了一种具有排气阀装置的食品处理系统的排气阀装置和干燥器。 干燥机包括具有输入端口和排出口的滚筒。 搅拌螺杆可旋转地设置在滚筒中，并且包括用于搅拌和粉碎食物垃圾的旋转叶片和用于支撑旋转叶片的旋转轴。 供电单元设置在滚筒的表面上，并向搅拌螺杆供电以旋转搅拌螺杆。 在鼓体的外表面上设置有加热器，并且当向加热器施加电力时，向鼓的内部空间提供高温热量，从而干燥食物废物。 排气装置安装在排出口的下表面以打开或关闭排出口。

    Methods of forming a trench having side surfaces including a uniform slope
    5.
    发明授权
    Methods of forming a trench having side surfaces including a uniform slope 有权
    形成具有包括均匀斜率的侧表面的沟槽的方法

    公开(公告)号：US07795151B2

    公开(公告)日：2010-09-14

    申请号：US11624410

    申请日：2007-01-18

    申请人： Ki-Chul Kim

    发明人： Ki-Chul Kim

    IPC分类号： H01L21/311

    CPC分类号： H01L21/76224

    摘要： Provided herein are methods of forming a trench including forming a mask layer on a substrate, forming a mask pattern to expose the substrate, using plasma to at least partially remove by-products produced during formation of the mask pattern; and etching the exposed substrate to form a trench having side surfaces including a uniform slope.

    摘要翻译： 本文提供了形成沟槽的方法，包括在衬底上形成掩模层，形成掩模图案以暴露衬底，使用等离子体至少部分地去除在形成掩模图案期间产生的副产物; 并蚀刻暴露的衬底以形成具有包括均匀斜率的侧表面的沟槽。

    Semiconductor Devices Including Multiple Stress Films in Interface Area
    6.
    发明申请
    Semiconductor Devices Including Multiple Stress Films in Interface Area 失效
    在接口区域包括多个应力薄膜的半导体器件

    公开(公告)号：US20100065919A1

    公开(公告)日：2010-03-18

    申请号：US12621079

    申请日：2009-11-18

    申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

    发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

    摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

    Non-volatile memory device and method of fabricating the same
    7.
    发明授权
    Non-volatile memory device and method of fabricating the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号：US07586137B2

    公开(公告)日：2009-09-08

    申请号：US11200491

    申请日：2005-08-09

    申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Sang-su Kim ,  Jin-hee Kim ,  Byou-ree Lim

    发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Sang-su Kim ,  Jin-hee Kim ,  Byou-ree Lim

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

    摘要： A non-volatile memory device having an asymmetric channel structure is provided. The non-volatile memory device includes a semiconductor substrate, a source region and a drain region which are formed in the semiconductor substrate and doped with n-type impurities, a trapping structure which includes a tunneling layer, which is disposed on a predetermined region of the semiconductor substrate and through which charge carriers are tunneled, and a charge trapping layer, which is formed on the tunneling layer and traps the tunneled charge carriers, a gate insulating layer which is formed on the trapping structure and the exposed semiconductor substrate, a gate electrode which is formed on the gate insulating layer, and a channel region which is formed between the source region and the drain region and includes a first channel region formed on a lower part of the trapping structure and a second channel region formed on a lower part of the gate insulating layer, the threshold voltage of the first channel region being lower than that of the second channel region.

    摘要翻译： 提供了具有非对称沟道结构的非易失性存储器件。 非易失性存储器件包括形成在半导体衬底中并掺杂有n型杂质的半导体衬底，源极区和漏极区，包括隧穿层的俘获结构，其被布置在 半导体衬底和通过其电荷载流子被隧道化;以及电荷俘获层，其形成在隧穿层上并俘获隧穿电荷载流子;形成在俘获结构和暴露的半导体衬底上的栅极绝缘层，栅极 形成在栅极绝缘层上的电极和形成在源极区域和漏极区域之间的沟道区域，并且包括形成在捕获结构的下部的第一沟道区域和形成在栅极绝缘层的下部的第二沟道区域 所述第一沟道区的阈值电压低于所述第二沟道区的阈值电压。

    PARALLEL PROCESSOR FOR EFFICIENT PROCESSING OF MOBILE MULTIMEDIA
    8.
    发明申请
    PARALLEL PROCESSOR FOR EFFICIENT PROCESSING OF MOBILE MULTIMEDIA 有权
    并行处理器对移动多媒体的高效处理

    公开(公告)号：US20080294875A1

    公开(公告)日：2008-11-27

    申请号：US12045844

    申请日：2008-03-11

    申请人： Chun Gi LYUH ,  Yil Suk YANG ,  Se Wan HEO ,  Soon Il YEO ,  Tae Moon ROH ,  Jong Dae KIM ,  Ki Chul KIM ,  Se Hoon YOO

    发明人： Chun Gi LYUH ,  Yil Suk YANG ,  Se Wan HEO ,  Soon Il YEO ,  Tae Moon ROH ,  Jong Dae KIM ,  Ki Chul KIM ,  Se Hoon YOO

    IPC分类号： G06F15/76 ,  G06F9/02

    CPC分类号： G06F15/8007

    摘要： Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.

    摘要翻译： 提供了一种用于支持浮点运算的并行处理器。 并行处理器具有灵活的结构，便于开发涉及多媒体计算的并行算法，需要较低的硬件成本，并且消耗低功耗。 为了支持浮点运算，并行处理器使用浮点累加器和浮点乘法的标志。 使用并行处理器，可以以低成本在三维（3D）图形处理中处理几何变换操作。 此外，可以通过分区单指令多数据（SIMD）方法和有条件执行指令的方法来最小化用于指令的总线宽度的成本。

    NON-VOLATILE MEMORY DEVICE WITH BURIED CONTROL GATE AND METHOD OF FABRICATING THE SAME
    9.
    发明申请
    NON-VOLATILE MEMORY DEVICE WITH BURIED CONTROL GATE AND METHOD OF FABRICATING THE SAME 失效
    带有控制门的非易失性存储器件及其制造方法

    公开(公告)号：US20080286927A1

    公开(公告)日：2008-11-20

    申请号：US12183553

    申请日：2008-07-31

    申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

    发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L29/42352 ,  H01L21/28282 ,  H01L29/7923 ,  Y10S438/954

    摘要： In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a trench formed in a semiconductor substrate, and forming charge storing regions in the semiconductor substrate on both sides of the control gate in a self-aligning manner, thereby allowing for multi-level cell operation.

    摘要翻译： 在具有埋地控制栅极的非易失性存储器件中，增加控制栅极的有效沟道长度以限制穿通，并且增加用于存储电荷的区域以获得有利的大容量。 一种制造存储器件的方法包括：在形成于半导体衬底中的沟槽内形成控制栅极，并以自对准的方式在控制栅极两侧的半导体衬底中形成电荷存储区域，从而允许多级 电池操作。