公开(公告)号：US20110023907A1

公开(公告)日：2011-02-03

申请号：US12834121

申请日：2010-07-12

申请人： Young Bang LEE ,  Kwang Kee CHAE ,  Ok Min MOON

发明人： Young Bang LEE ,  Kwang Kee CHAE ,  Ok Min MOON

IPC分类号： C23G1/02

CPC分类号： C23G1/103 ,  H01L21/02068 ,  H01L21/0209 ,  Y10S134/902 ,  Y10S438/906

摘要： A method for manufacturing a semiconductor device includes the step of conducting a cleaning process for a wafer formed with copper wiring lines to remove contaminations produced on a back surface of the wafer. The cleaning process is conducted by injecting onto the back surface of the wafer an etchant for removing contaminations and simultaneously injecting onto a front surface of the wafer a reductant containing hydrogen.

摘要翻译： 一种制造半导体器件的方法包括对由铜布线形成的晶片进行清洁处理以除去晶片背面产生的污染物的步骤。 通过在晶片的背面注入用于去除污染物的蚀刻剂并同时向晶片的前表面注入含有氢的还原剂来进行清洁过程。

公开(公告)号：US20100164051A1

公开(公告)日：2010-07-01

申请号：US12398323

申请日：2009-03-05

申请人： Kwang Kee CHAE ,  Jae Seon YU ,  Jae Kyun LEE

发明人： Kwang Kee CHAE ,  Jae Seon YU ,  Jae Kyun LEE

IPC分类号： H01L23/58 ,  H01L21/76

CPC分类号： H01L21/823481 ,  H01L21/823437

摘要： A semiconductor device includes a semiconductor substrate with an isolation layer formed in the semiconductor substrate to delimit active regions. Recess patterns for gates are defined in the active regions and the isolation layer. Gate patterns are formed in and over the recess patterns for gates, and a gate spacer is formed to cover the gate patterns. The recess patterns for gates have a first depth in the active regions and a second depth, which is greater than the first depth, in the isolation layer. Gaps are created between the gate patterns and upper parts of the recess patterns for gates that are defined in the isolation layer. The gate spacer fills the gaps and protects the gate spacer so as to prevent bridging.

摘要翻译： 半导体器件包括半导体衬底，其具有形成在半导体衬底中以限定有源区的隔离层。 在活动区域​​和隔离层中限定栅极的凹槽图案。 栅极图案形成在用于栅极的凹槽图案中和上方，并且形成栅极间隔物以覆盖栅极图案。 栅极的凹槽图案在有源区域中具有第一深度，并且在隔离层中具有大于第一深度的第二深度。 在隔离层中限定的门的凹槽图案的栅极图案和上部之间产生间隙。 栅极间隔物填充间隙并保护栅极间隔物以防止桥接。

公开(公告)号：US08841198B2

公开(公告)日：2014-09-23

申请号：US12167322

申请日：2008-07-03

申请人： Hyung Hwan Kim ,  Kwang Kee Chae ,  Jong Goo Jung ,  Ok Min Moon ,  Young Bang Lee ,  Sung Eun Park

发明人： Hyung Hwan Kim ,  Kwang Kee Chae ,  Jong Goo Jung ,  Ok Min Moon ,  Young Bang Lee ,  Sung Eun Park

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76232

摘要： An isolation layer of a semiconductor device and a process for forming the same is described herein. The isolation layer includes a trench that is defined and formed in a semiconductor substrate. A first liner nitride layer is formed on the surface of the trench and a flowable insulation layer is formed in the trench including the first liner nitride layer. The flowable insulation layer is formed such to define a recess in the trench. A second liner nitride layer is formed on the recess including the flowable insulation layer and the first liner nitride layer. Finally, an insulation layer is formed in the recess on the second liner nitride layer to completely fill the trench.

摘要翻译： 本文描述了半导体器件的隔离层及其形成工艺。 隔离层包括限定并形成在半导体衬底中的沟槽。 第一衬里氮化物层形成在沟槽的表面上，并且在包括第一衬里氮化物层的沟槽中形成可流动的绝缘层。 可流动绝缘层形成为在沟槽中限定凹部。 在包括可流动绝缘层和第一衬里氮化物层的凹部上形成第二衬里氮化物层。 最后，在第二衬里氮化物层上的凹槽中形成绝缘层以完全填充沟槽。

公开(公告)号：US08007594B2

公开(公告)日：2011-08-30

申请号：US12834121

申请日：2010-07-12

申请人： Young Bang Lee ,  Kwang Kee Chae ,  Ok Min Moon

发明人： Young Bang Lee ,  Kwang Kee Chae ,  Ok Min Moon

IPC分类号： C23G1/02

CPC分类号： C23G1/103 ,  H01L21/02068 ,  H01L21/0209 ,  Y10S134/902 ,  Y10S438/906

摘要： A method for manufacturing a semiconductor device includes the step of conducting a cleaning process for a wafer formed with copper wiring lines to remove contaminations produced on a back surface of the wafer. The cleaning process is conducted by injecting onto the back surface of the wafer an etchant for removing contaminations and simultaneously injecting onto a front surface of the wafer a reductant containing hydrogen.

摘要翻译： 一种制造半导体器件的方法包括对由铜布线形成的晶片进行清洁处理以除去晶片背面产生的污染物的步骤。 通过在晶片的背面注入用于去除污染物的蚀刻剂并同时向晶片的前表面注入含有氢的还原剂来进行清洁过程。

公开(公告)号：US20080003792A1

公开(公告)日：2008-01-03

申请号：US11647865

申请日：2006-12-29

申请人： Kwang Kee Chae

发明人： Kwang Kee Chae

IPC分类号： H01L21/467

CPC分类号： H01L21/02071 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/32139

摘要： A gate of a semiconductor device is formed by forming sequentially a gate insulation layer, a polysilicon layer, metal based layer and a hard mask on a semiconductor substrate; etching primarily the metal based layer and a partial thickness of the polysilicon layer using the hard mask as an etch mask; cleaning primarily surfaces of the etched metal based layer and polysilicon layer with an HF-containing solution; and cleaning secondarily the primarily cleaned surfaces using ozone.

摘要翻译： 半导体器件的栅极通过在半导体衬底上依次形成栅极绝缘层，多晶硅层，金属基层和硬掩模而形成; 使用硬掩模作为蚀刻掩模主要蚀刻金属基层和多晶硅层的部分厚度; 用含HF的溶液主要清洗被蚀刻的金属基层和多晶硅层的表面; 并使用臭氧二次清洁主要清洁的表面。

公开(公告)号：US07855109B2

公开(公告)日：2010-12-21

申请号：US12345755

申请日：2008-12-30

申请人： Hyung Hwan Kim ,  Kwang Kee Chae ,  Jong Goo Jung ,  Ok Min Moon ,  Young Bang Lee ,  Sung Eun Park

发明人： Hyung Hwan Kim ,  Kwang Kee Chae ,  Jong Goo Jung ,  Ok Min Moon ,  Young Bang Lee ,  Sung Eun Park

IPC分类号： H01L21/337

CPC分类号： H01L21/76232

摘要： A method for manufacturing a semiconductor device according to the present invention, comprising the steps of: forming a screen oxide layer over the surface of an active region of a semiconductor substrate in which an isolation structure defining the active region is formed; forming a first recess pattern in the active region and a second recess pattern in the isolation structure by etching a gate forming area in the active region and the isolation structure part extended thereto; removing the screen oxide film and simultaneously expanding the width of the second recess pattern; forming a first insulation dielectric layer over the resultant of the substrate having the second recess pattern with the expanded width so that the first insulation dielectric layer is blocked at the upper end thereof in the first recess pattern and it is deposited along the profile in the second recess pattern; forming a second insulation dielectric layer over the first insulation dielectric layer so that the second recess patter is not filled; forming a third insulation dielectric layer over the second insulation dielectric layer so that the second recess pattern is filled; and removing the third, second, and first insulation dielectric layers formed over the active region including the first recess pattern and the isolation structure between the second recess patterns.

摘要翻译： 一种根据本发明的半导体器件的制造方法，包括以下步骤：在其中形成限定有源区的隔离结构的半导体衬底的有源区的表面上形成屏蔽氧化物层; 通过蚀刻有源区域中的栅极形成区域和延伸到其中的隔离结构部分，在有源区域中形成第一凹槽图案和隔离结构中的第二凹陷图案; 去除屏幕氧化膜并同时扩大第二凹槽图案的宽度; 在具有第二凹槽图案的基底的结果上形成第一绝缘电介质层，其具有扩展的宽度，使得第一绝缘电介质层在其第一凹槽图案的上端处被阻挡，并且沿着第二凹部图案 休闲模式; 在所述第一绝缘电介质层上形成第二绝缘电介质层，使得所述第二凹槽图案不被填充; 在所述第二绝缘电介质层上形成第三绝缘电介质层，使得所述第二凹槽图案被填充; 以及去除在包括第一凹槽图案的有源区域和在第二凹槽图案之间的隔离结构之间形成的第三绝缘介电层和第二绝缘介电层。

公开(公告)号：US20100159683A1

公开(公告)日：2010-06-24

申请号：US12494055

申请日：2009-06-29

申请人： Jin Yul Lee ,  Bong Ho Choi ,  Kwang Kee Chae ,  Dong Seok Kim ,  Jae Seon Yu ,  Hyung Hwan Kim ,  Jae Kyun Lee

发明人： Jin Yul Lee ,  Bong Ho Choi ,  Kwang Kee Chae ,  Dong Seok Kim ,  Jae Seon Yu ,  Hyung Hwan Kim ,  Jae Kyun Lee

IPC分类号： H01L21/28 ,  H01L21/306

CPC分类号： H01L21/3185 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28123 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/3141 ,  H01L21/76232 ,  H01L29/1037 ,  H01L29/66621

摘要： A method for fabricating a semiconductor device having a recess channel includes forming an isolation layer that delimits an active region over a semiconductor substrate; exposing a region to be formed with a bulb recess trench over the semiconductor substrate; forming an upper trench by etching the exposed portion of the semiconductor substrate; forming, on a side wall of the upper trench, a silicon nitride barrier layer that exposes a bottom face of the upper trench but blocks a side wall of the upper trench; forming a lower trench of a bulb type by etching the exposed bottom face of the upper trench using the etch barrier layer as an etch mask, to form the bulb recess trench including the upper trench and the lower trench; forming a fin-structured bottom protrusion part including an upper face and a side face by etching the isolation layer so that the isolation layer has a surface lower than the bottom face of the lower trench; and forming a gate stack overlapped with the bulb recess trench and the bottom protrusion part.

摘要翻译： 一种制造具有凹槽通道的半导体器件的方法包括：形成限定半导体衬底上的有源区的隔离层; 在半导体衬底上露出要形成有灯泡凹槽的区域; 通过蚀刻半导体衬底的暴露部分形成上沟槽; 在所述上沟槽的侧壁上形成暴露所述上沟槽的底面但阻挡所述上沟槽的侧壁的氮化硅阻挡层; 通过使用蚀刻阻挡层作为蚀刻掩模蚀刻上沟槽的暴露的底面来形成灯泡类型的下沟槽，以形成包括上沟槽和下沟槽的灯泡凹槽; 通过蚀刻隔离层形成包括上表面和侧面的翅片结构的底部突出部分，使得隔离层具有比下沟槽的底面低的表面; 以及形成与灯泡凹槽和底部突出部重叠的栅极叠层。

公开(公告)号：US07923784B2

公开(公告)日：2011-04-12

申请号：US12398323

申请日：2009-03-05

申请人： Kwang Kee Chae ,  Jae Seon Yu ,  Jae Kyun Lee

发明人： Kwang Kee Chae ,  Jae Seon Yu ,  Jae Kyun Lee

IPC分类号： H01L21/70 ,  H01L27/088 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L21/823481 ,  H01L21/823437

摘要： A semiconductor device includes a semiconductor substrate with an isolation layer formed in the semiconductor substrate to delimit active regions. Recess patterns for gates are defined in the active regions and the isolation layer. Gate patterns are formed in and over the recess patterns for gates, and a gate spacer is formed to cover the gate patterns. The recess patterns for gates have a first depth in the active regions and a second depth, which is greater than the first depth, in the isolation layer. Gaps are created between the gate patterns and upper parts of the recess patterns for gates that are defined in the isolation layer. The gate spacer fills the gaps and protects the gate spacer so as to prevent bridging.

摘要翻译： 半导体器件包括半导体衬底，其具有形成在半导体衬底中以限定有源区的隔离层。 在活动区域​​和隔离层中限定栅极的凹槽图案。 栅极图案形成在用于栅极的凹槽图案中和上方，并且形成栅极间隔物以覆盖栅极图案。 栅极的凹槽图案在有源区域中具有第一深度，并且在隔离层中具有大于第一深度的第二深度。 在隔离层中限定的门的凹槽图案的栅极图案和上部之间产生间隙。 栅极间隔物填充间隙并保护栅极间隔物以防止桥接。

公开(公告)号：US20100151656A1

公开(公告)日：2010-06-17

申请号：US12345755

申请日：2008-12-30

申请人： Hyung Hwan KIM ,  Kwang Kee CHAE ,  Jong Goo JUNG ,  Ok Min MOON ,  Young Bang LEE ,  Sung Eun PARK

发明人： Hyung Hwan KIM ,  Kwang Kee CHAE ,  Jong Goo JUNG ,  Ok Min MOON ,  Young Bang LEE ,  Sung Eun PARK

IPC分类号： H01L21/762

CPC分类号： H01L21/76232

摘要： A method for manufacturing a semiconductor device according to the present invention, comprising the steps of: forming a screen oxide layer over the surface of an active region of a semiconductor substrate in which an isolation structure defining the active region is formed; forming a first recess pattern in the active region and a second recess pattern in the isolation structure by etching a gate forming area in the active region and the isolation structure part extended thereto; removing the screen oxide film and simultaneously expanding the width of the second recess pattern; forming a first insulation dielectric layer over the resultant of the substrate having the second recess pattern with the expanded width so that the first insulation dielectric layer is blocked at the upper end thereof in the first recess pattern and it is deposited along the profile in the second recess pattern; forming a second insulation dielectric layer over the first insulation dielectric layer so that the second recess patter is not filled; forming a third insulation dielectric layer over the second insulation dielectric layer so that the second recess pattern is filled; and removing the third, second, and first insulation dielectric layers formed over the active region including the first recess pattern and the isolation structure between the second recess patterns.

摘要翻译： 一种根据本发明的半导体器件的制造方法，包括以下步骤：在其中形成限定有源区的隔离结构的半导体衬底的有源区的表面上形成屏蔽氧化物层; 通过蚀刻有源区域中的栅极形成区域和延伸到其中的隔离结构部分，在有源区域中形成第一凹槽图案和隔离结构中的第二凹陷图案; 去除屏幕氧化膜并同时扩大第二凹槽图案的宽度; 在具有第二凹槽图案的基底的结果上形成第一绝缘电介质层，其具有扩展的宽度，使得第一绝缘电介质层在其第一凹槽图案的上端处被阻挡，并且沿着第二凹部图案 休闲模式; 在所述第一绝缘电介质层上形成第二绝缘电介质层，使得所述第二凹槽图案不被填充; 在所述第二绝缘电介质层上形成第三绝缘电介质层，使得所述第二凹槽图案被填充; 以及去除在包括第一凹槽图案的有源区域和在第二凹槽图案之间的隔离结构之间形成的第三绝缘介电层和第二绝缘介电层。

公开(公告)号：US20090267199A1

公开(公告)日：2009-10-29

申请号：US12167322

申请日：2008-07-03

申请人： Hyung Hwan KIM ,  Kwang Kee CHAE ,  Jong Goo JUNG ,  Ok Min MOON ,  Young Bang LEE ,  Sung Eun PARK

发明人： Hyung Hwan KIM ,  Kwang Kee CHAE ,  Jong Goo JUNG ,  Ok Min MOON ,  Young Bang LEE ,  Sung Eun PARK

IPC分类号： H01L21/762 ,  H01L23/58

CPC分类号： H01L21/76232

摘要： An isolation layer of a semiconductor device and a process for forming the same is described herein. The isolation layer includes a trench that is defined and formed in a semiconductor substrate. A first liner nitride layer is formed on the surface of the trench and a flowable insulation layer is formed in the trench including the first liner nitride layer. The flowable insulation layer is formed such to define a recess in the trench. A second liner nitride layer is formed on the recess including the flowable insulation layer and the first liner nitride layer. Finally, an insulation layer is formed in the recess on the second liner nitride layer to completely fill the trench.

摘要翻译： 本文描述了半导体器件的隔离层及其形成工艺。 隔离层包括限定并形成在半导体衬底中的沟槽。 第一衬里氮化物层形成在沟槽的表面上，并且在包括第一衬里氮化物层的沟槽中形成可流动的绝缘层。 可流动绝缘层形成为在沟槽中限定凹部。 在包括可流动绝缘层和第一衬里氮化物层的凹部上形成第二衬里氮化物层。 最后，在第二衬里氮化物层上的凹槽中形成绝缘层以完全填充沟槽。