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    NON-VOLATILE MEMORY SYSTEMS
    2.
    发明申请
    NON-VOLATILE MEMORY SYSTEMS 有权
    非易失性存储器系统

    公开(公告)号：US20130058169A1

    公开(公告)日：2013-03-07

    申请号：US13548506

    申请日：2012-07-13

    申请人： Bong-Yong Lee ,  Jung-In Han ,  Hae-Bum Lee ,  Sang-Eun Lee ,  Jung-Ro Ahn ,  Kyung-Jun Shin ,  Tae-Hyun Yoon

    发明人： Bong-Yong Lee ,  Jung-In Han ,  Hae-Bum Lee ,  Sang-Eun Lee ,  Jung-Ro Ahn ,  Kyung-Jun Shin ,  Tae-Hyun Yoon

    IPC分类号： G11C16/28 ,  G11C16/06

    CPC分类号： G11C16/06 ,  G11C16/28

    摘要： In a non-volatile memory system, a plurality of main memory cells for storing data is arranged in a data cell array and a plurality of reference memory cells is arranged in a reference cell array. The reference cell array includes first reference word lines connected to first reference memory cells and extending, second reference word lines connected to second reference memory cells and extending alternately with the first reference word lines, reference bit lines to which the first and the second reference memory cells are alternately connected in a line and a combined cell having a pair of the first and second reference memory cells and generating a reference signal for processing the data. The first and the second reference memory cells have different cell characteristics. The stability of the reference signal is improved irrespective of the differentiation of the first and the second reference memory cells.

    摘要翻译： 在非易失性存储器系统中，用于存储数据的多个主存储单元被布置在数据单元阵列中，并且多个参考存储单元被布置在参考单元阵列中。 参考单元阵列包括连接到第一参考存储器单元的第一参考字线和连接到第二参考存储器单元并与第一参考字线交替延伸的第二参考字线，第一和第二参考存储器 单元交替地连接在一行中，并且组合单元具有一对第一和第二参考存储单元，并产生用于处理数据的参考信号。 第一和第二参考存储单元具有不同的单元特性。 无论第一和第二参考存储单元的区别如何，参考信号的稳定性得到改善。

    VERTICAL MEMORY DEVICE
    3.
    发明申请
    VERTICAL MEMORY DEVICE 审中-公开

    公开(公告)号：US20180122819A1

    公开(公告)日：2018-05-03

    申请号：US15465355

    申请日：2017-03-21

    申请人： JAE JOO SHIM ,  SEONG SOON CHO ,  JI HYE KIM ,  KYUNG JUN SHIN

    发明人： JAE JOO SHIM ,  SEONG SOON CHO ,  JI HYE KIM ,  KYUNG JUN SHIN

    IPC分类号： H01L27/11568 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11573

    摘要： A vertical memory device includes a substrate having a cell array region and a connection region positioned on an exterior of the cell array region. Gate electrode layers are stacked on the cell array region and the connection region of the substrate, forming a stepped structure in the connection region. Channel structures are disposed in the cell array region, extending in a direction perpendicular to an upper surface of the substrate, while passing through the gate electrode layers. Dummy channel structures are disposed in the connection region, extending in the same direction as the channel structures, while passing through the gate electrode layers forming the stepped structure. First semiconductor patterns are disposed below the channel structures, and second semiconductor patterns are disposed below the dummy channel structures. The first and second semiconductor patterns include polycrystalline semiconductor materials.

    Vertical memory device
    4.
    发明授权
    Vertical memory device 有权

    公开(公告)号：US10790294B2

    公开(公告)日：2020-09-29

    申请号：US15465355

    申请日：2017-03-21

    申请人： Jae Joo Shim ,  Seong Soon Cho ,  Ji Hye Kim ,  Kyung Jun Shin

    发明人： Jae Joo Shim ,  Seong Soon Cho ,  Ji Hye Kim ,  Kyung Jun Shin

    IPC分类号： H01L27/1157 ,  H01L27/11568 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11573

    摘要： A vertical memory device includes a substrate having a cell array region and a connection region positioned on an exterior of the cell array region. Gate electrode layers are stacked on the cell array region and the connection region of the substrate, forming a stepped structure in the connection region. Channel structures are disposed in the cell array region, extending in a direction perpendicular to an upper surface of the substrate, while passing through the gate electrode layers. Dummy channel structures are disposed in the connection region, extending in the same direction as the channel structures, while passing through the gate electrode layers forming the stepped structure. First semiconductor patterns are disposed below the channel structures, and second semiconductor patterns are disposed below the dummy channel structures. The first and second semiconductor patterns include polycrystalline semiconductor materials.

    NAND-TYPE FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME
    6.
    发明申请
    NAND-TYPE FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME 审中-公开
    NAND型闪存存储器件及其编程方法

    公开(公告)号：US20150294726A1

    公开(公告)日：2015-10-15

    申请号：US14672372

    申请日：2015-03-30

    申请人： JAE-SUNG SIM ,  JOO-HEON KANG ,  KYUNG-JUN SHIN

    发明人： JAE-SUNG SIM ,  JOO-HEON KANG ,  KYUNG-JUN SHIN

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C16/10 ,  G11C16/0483

    摘要： A NAND-type flash memory device and method for programming the NAND-type flash memory device are provided. The method may include applying a voltage of 0 V to an unselected string select line, applying the voltage of 0 V to a selected bit line, applying a supply voltage to a selected string select line, and applying a dummy pass voltage to a dummy word line, the dummy pass voltage being in a range between 0 V to a pass voltage. The method may further include applying the supply voltage to an unselected bit line, applying the pass voltage to a selected word line, applying the pass voltage to an unselected word line; and applying a program voltage to the selected word line.

    摘要翻译： 提供了NAND​​型闪速存储器件和用于对NAND型闪速存储器件进行编程的方法。 该方法可以包括向未选择的串选择线施加0V的电压，将0V的电压施加到所选择的位线，向所选择的串选择线施加电源电压，并将虚拟电压施加到虚拟字 虚拟通过电压在0V至通过电压之间的范围内。 该方法可以进一步包括将电源电压施加到未选择的位线，将通过电压施加到所选择的字线，将通过电压施加到未选择的字线; 以及将程序电压施加到所选择的字线。

    Non-volatile memory systems having at least one pair of memory cells
    10.
    发明授权
    Non-volatile memory systems having at least one pair of memory cells 有权
    具有至少一对存储单元的非易失性存储器系统

    公开(公告)号：US08897076B2

    公开(公告)日：2014-11-25

    申请号：US13548506

    申请日：2012-07-13

    申请人： Bong-Yong Lee ,  Jung-In Han ,  Hae-Bum Lee ,  Sang-Eun Lee ,  Jung-Ro Ahn ,  Kyung-Jun Shin ,  Tae-Hyun Yoon

    发明人： Bong-Yong Lee ,  Jung-In Han ,  Hae-Bum Lee ,  Sang-Eun Lee ,  Jung-Ro Ahn ,  Kyung-Jun Shin ,  Tae-Hyun Yoon

    IPC分类号： G11C16/28 ,  G11C16/06

    CPC分类号： G11C16/06 ,  G11C16/28

    摘要： In a non-volatile memory system, a plurality of main memory cells for storing data is arranged in a data cell array and a plurality of reference memory cells is arranged in a reference cell array. The reference cell array includes first reference word lines connected to first reference memory cells and extending, second reference word lines connected to second reference memory cells and extending alternately with the first reference word lines, reference bit lines to which the first and the second reference memory cells are alternately connected in a line and a combined cell having a pair of the first and second reference memory cells and generating a reference signal for processing the data. The first and the second reference memory cells have different cell characteristics. The stability of the reference signal is improved irrespective of the differentiation of the first and the second reference memory cells.

    摘要翻译： 在非易失性存储器系统中，用于存储数据的多个主存储单元被布置在数据单元阵列中，并且多个参考存储单元被布置在参考单元阵列中。 参考单元阵列包括连接到第一参考存储器单元的第一参考字线和连接到第二参考存储器单元并与第一参考字线交替延伸的第二参考字线，第一和第二参考存储器 单元交替地连接在一行中，并且组合单元具有一对第一和第二参考存储单元，并产生用于处理数据的参考信号。 第一和第二参考存储单元具有不同的单元特性。 无论第一和第二参考存储单元的区别如何，参考信号的稳定性得到改善。