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    Non-volatile memory systems having at least one pair of memory cells
    1.
    发明授权
    Non-volatile memory systems having at least one pair of memory cells 有权
    具有至少一对存储单元的非易失性存储器系统

    公开(公告)号：US08897076B2

    公开(公告)日：2014-11-25

    申请号：US13548506

    申请日：2012-07-13

    申请人： Bong-Yong Lee ,  Jung-In Han ,  Hae-Bum Lee ,  Sang-Eun Lee ,  Jung-Ro Ahn ,  Kyung-Jun Shin ,  Tae-Hyun Yoon

    发明人： Bong-Yong Lee ,  Jung-In Han ,  Hae-Bum Lee ,  Sang-Eun Lee ,  Jung-Ro Ahn ,  Kyung-Jun Shin ,  Tae-Hyun Yoon

    IPC分类号： G11C16/28 ,  G11C16/06

    CPC分类号： G11C16/06 ,  G11C16/28

    摘要： In a non-volatile memory system, a plurality of main memory cells for storing data is arranged in a data cell array and a plurality of reference memory cells is arranged in a reference cell array. The reference cell array includes first reference word lines connected to first reference memory cells and extending, second reference word lines connected to second reference memory cells and extending alternately with the first reference word lines, reference bit lines to which the first and the second reference memory cells are alternately connected in a line and a combined cell having a pair of the first and second reference memory cells and generating a reference signal for processing the data. The first and the second reference memory cells have different cell characteristics. The stability of the reference signal is improved irrespective of the differentiation of the first and the second reference memory cells.

    摘要翻译： 在非易失性存储器系统中，用于存储数据的多个主存储单元被布置在数据单元阵列中，并且多个参考存储单元被布置在参考单元阵列中。 参考单元阵列包括连接到第一参考存储器单元的第一参考字线和连接到第二参考存储器单元并与第一参考字线交替延伸的第二参考字线，第一和第二参考存储器 单元交替地连接在一行中，并且组合单元具有一对第一和第二参考存储单元，并产生用于处理数据的参考信号。 第一和第二参考存储单元具有不同的单元特性。 无论第一和第二参考存储单元的区别如何，参考信号的稳定性得到改善。

    NON-VOLATILE MEMORY SYSTEMS
    2.
    发明申请
    NON-VOLATILE MEMORY SYSTEMS 有权
    非易失性存储器系统

    公开(公告)号：US20130058169A1

    公开(公告)日：2013-03-07

    申请号：US13548506

    申请日：2012-07-13

    申请人： Bong-Yong Lee ,  Jung-In Han ,  Hae-Bum Lee ,  Sang-Eun Lee ,  Jung-Ro Ahn ,  Kyung-Jun Shin ,  Tae-Hyun Yoon

    发明人： Bong-Yong Lee ,  Jung-In Han ,  Hae-Bum Lee ,  Sang-Eun Lee ,  Jung-Ro Ahn ,  Kyung-Jun Shin ,  Tae-Hyun Yoon

    IPC分类号： G11C16/28 ,  G11C16/06

    CPC分类号： G11C16/06 ,  G11C16/28

    摘要： In a non-volatile memory system, a plurality of main memory cells for storing data is arranged in a data cell array and a plurality of reference memory cells is arranged in a reference cell array. The reference cell array includes first reference word lines connected to first reference memory cells and extending, second reference word lines connected to second reference memory cells and extending alternately with the first reference word lines, reference bit lines to which the first and the second reference memory cells are alternately connected in a line and a combined cell having a pair of the first and second reference memory cells and generating a reference signal for processing the data. The first and the second reference memory cells have different cell characteristics. The stability of the reference signal is improved irrespective of the differentiation of the first and the second reference memory cells.

    摘要翻译： 在非易失性存储器系统中，用于存储数据的多个主存储单元被布置在数据单元阵列中，并且多个参考存储单元被布置在参考单元阵列中。 参考单元阵列包括连接到第一参考存储器单元的第一参考字线和连接到第二参考存储器单元并与第一参考字线交替延伸的第二参考字线，第一和第二参考存储器 单元交替地连接在一行中，并且组合单元具有一对第一和第二参考存储单元，并产生用于处理数据的参考信号。 第一和第二参考存储单元具有不同的单元特性。 无论第一和第二参考存储单元的区别如何，参考信号的稳定性得到改善。

    Non-Volatile Memory Device
    5.
    发明申请
    Non-Volatile Memory Device 审中-公开
    非易失性存储器件

    公开(公告)号：US20120146120A1

    公开(公告)日：2012-06-14

    申请号：US13236368

    申请日：2011-09-19

    申请人： Jung-In Han ,  Sang Eun Lee ,  Hyouk Sang Yun ,  Tong-Hyun Shin ,  June-Ui Song ,  Hae-Bum Lee ,  Bong-Yong Lee

    发明人： Jung-In Han ,  Sang Eun Lee ,  Hyouk Sang Yun ,  Tong-Hyun Shin ,  June-Ui Song ,  Hae-Bum Lee ,  Bong-Yong Lee

    IPC分类号： H01L29/78 ,  H01L27/088

    CPC分类号： H01L27/11521 ,  H01L27/11519

    摘要： A non-volatile memory device includes memory cell active regions and common source active regions extending in parallel on a semiconductor substrate, a self aligned source active region disposed on the semiconductor substrate that intersects the memory cell active regions and the common source active regions and connects the memory cell active regions to the common source active regions, word lines disposed on the memory cell active regions and the common source active regions that intersect the memory cell active regions and the common source active regions, and memory cell transistors formed by the intersection of the word lines and the memory cell active regions, and common source line transistors formed by the intersection of the word lines and the common source active regions, wherein source and drain regions of each of the common source line transistors are separated from each other in the semiconductor substrate.

    摘要翻译： 非易失性存储器件包括在半导体衬底上平行延伸的存储器单元有源区和共同源极有源区，设置在半导体衬底上的自对准源有源区，与存储单元有源区和公共源有源区相交，并连接 存储单元有效区域到公共源极活性区域，位于存储单元有源区域上的字线和与存储单元有源区域和公共源极有源区域相交的公共源极有源区， 字线和存储单元有源区，以及由字线和公共源有源区的交叉形成的公共源极线晶体管，其中每个公共源极线晶体管的源极和漏极区彼此分离 半导体衬底。

    Semiconductor memory device and method for repairing the same
    8.
    发明申请
    Semiconductor memory device and method for repairing the same 有权
    半导体存储器件及其修复方法

    公开(公告)号：US20080137454A1

    公开(公告)日：2008-06-12

    申请号：US12000208

    申请日：2007-12-11

    申请人： Bong-Yong Lee ,  Heon-Kyu Lee ,  Kwang-Soo Kim ,  Sang-Youl Kwon

    发明人： Bong-Yong Lee ,  Heon-Kyu Lee ,  Kwang-Soo Kim ,  Sang-Youl Kwon

    IPC分类号： G11C29/00

    CPC分类号： G11C29/808 ,  G11C29/846

    摘要： A semiconductor memory device includes a main cell array region, a first redundancy cell array region and a first dummy cell array region that are formed at one side of the main cell array region, and a second redundancy cell array region and a second dummy cell array region that are formed at the other side of the main cell array region. The first redundancy cell array region includes a first redundancy bitline, and the first dummy cell array region includes first dummy bitlines. The second redundancy cell array region includes a second redundancy bitline, and the second dummy cell array region includes second dummy bitlines. The first and second redundancy cell array regions are disposed closer to the main cell array region than the first and second dummy cell array regions.

    摘要翻译： 半导体存储器件包括形成在主单元阵列区域的一侧的主单元阵列区域，第一冗余单元阵列区域和第一虚设单元阵列区域，以及第二冗余单元阵列区域和第二虚设单元阵列 区域，其形成在主单元阵列区域的另一侧。 第一冗余单元阵列区域包括第一冗余位线，并且第一虚设单元阵列区域包括第一虚拟位线。 第二冗余单元阵列区域包括第二冗余位线，并且第二虚设单元阵列区域包括第二虚拟位线。 第一和第二冗余单元阵列区域比第一和第二虚设单元阵列区域更靠近主单元阵列区域设置。