公开(公告)号：US09449870B2

公开(公告)日：2016-09-20

申请号：US14943532

申请日：2015-11-17

申请人： Dongseog Eun ,  Young-Ho Lee ,  Joonhee Lee ,  Seok-won Lee ,  Yoocheol Shin

发明人： Dongseog Eun ,  Young-Ho Lee ,  Joonhee Lee ,  Seok-won Lee ,  Yoocheol Shin

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L23/498 ,  H01L27/115 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/441 ,  H01L27/24

CPC分类号： H01L23/498 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/441 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/49844 ,  H01L23/5226 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.

公开(公告)号：US20160099170A1

公开(公告)日：2016-04-07

申请号：US14943532

申请日：2015-11-17

申请人： Dongseog EUN ,  Young-Ho LEE ,  Joonhee LEE ,  Seok-won LEE ,  Yoocheol SHIN

发明人： Dongseog EUN ,  Young-Ho LEE ,  Joonhee LEE ,  Seok-won LEE ,  Yoocheol SHIN

IPC分类号： H01L21/768 ,  H01L27/24 ,  H01L21/3213 ,  H01L27/115 ,  H01L21/311

CPC分类号： H01L23/498 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/441 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/49844 ,  H01L23/5226 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.

摘要翻译： 提供了形成由此制造的电极堆叠和三维半导体器件的方法。 该装置可以包括依次层叠在基板上以构成电极结构的电极。 每个电极可以包括从位于其上的一个电极的侧壁水平和向外突出的连接部分和具有与位于其上的电极之一的侧壁共面的对准部分。 这里，彼此垂直相邻设置的电极中的至少两个可以以这样的方式设置，使得其对准的部分具有基本上对准以彼此共面的侧壁。

公开(公告)号：US09230904B2

公开(公告)日：2016-01-05

申请号：US13973627

申请日：2013-08-22

申请人： Dongseog Eun ,  Young-Ho Lee ,  Joonhee Lee ,  Seok-won Lee ,  Yoocheol Shin

发明人： Dongseog Eun ,  Young-Ho Lee ,  Joonhee Lee ,  Seok-won Lee ,  Yoocheol Shin

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L27/115

CPC分类号： H01L23/498 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/441 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/49844 ,  H01L23/5226 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.

摘要翻译： 提供了形成由此制造的电极堆叠和三维半导体器件的方法。 该装置可以包括依次层叠在基板上以构成电极结构的电极。 每个电极可以包括从位于其上的一个电极的侧壁水平和向外突出的连接部分和具有与位于其上的电极之一的侧壁共面的对准部分。 这里，彼此垂直相邻设置的电极中的至少两个可以以这样的方式设置，使得其对准的部分具有基本上对准以彼此共面的侧壁。

公开(公告)号：US20170110543A1

公开(公告)日：2017-04-20

申请号：US15260135

申请日：2016-09-08

申请人： KYUNG-JUN SHIN ,  BYOUNGIL LEE ,  DONGSEOG EUN ,  HYUNKOOK LEE ,  SEONG SOON CHO

发明人： KYUNG-JUN SHIN ,  BYOUNGIL LEE ,  DONGSEOG EUN ,  HYUNKOOK LEE ,  SEONG SOON CHO

IPC分类号： H01L29/10 ,  H01L27/115

CPC分类号： H01L29/1083 ,  H01L21/764 ,  H01L27/1157 ,  H01L27/11582

摘要： A three-dimensional (3D) semiconductor device includes a plurality of gate electrodes stacked on a substrate in a direction normal to a top surface of the substrate, a channel structure passing through the gate electrodes and connected to the substrate, and a void disposed in the substrate and positioned below the channel structure.

公开(公告)号：US20160133330A1

公开(公告)日：2016-05-12

申请号：US14887454

申请日：2015-10-20

申请人： BYEONG-IN CHOE ,  MINCHEOL PARK ,  DONGSEOG EUN ,  EUNSUK CHO

发明人： BYEONG-IN CHOE ,  MINCHEOL PARK ,  DONGSEOG EUN ,  EUNSUK CHO

IPC分类号： G11C16/14 ,  G11C16/26 ,  G11C16/08 ,  G11C16/32

CPC分类号： G11C16/14 ,  G11C7/04 ,  G11C16/32

摘要： An erase method of a nonvolatile memory device includes applying an erase voltage to a substrate; sensing a temperature of a memory cell array; setting a delay time based on the temperature of the memory cell array, wherein the delay time starts in response to the erase voltage being applied to the substrate; applying a ground voltage to a ground selection line connected to a ground selection transistor during the delay time; and increasing a voltage of the ground selection line after the delay time.

摘要翻译： 非易失性存储器件的擦除方法包括向衬底施加擦除电压; 感测存储单元阵列的温度; 基于所述存储单元阵列的温度来设置延迟时间，其中所述延迟时间响应于所述擦除电压被施加到所述衬底而开始; 在延迟时间内将接地电压施加到接地选择晶体管的接地选择线; 并在延迟时间后增加接地选择线的电压。

公开(公告)号：US20140054787A1

公开(公告)日：2014-02-27

申请号：US13973627

申请日：2013-08-22

申请人： Dongseog EUN ,  Young-Ho LEE ,  Joonhee LEE ,  Seok-won LEE ,  Yoocheol SHIN

发明人： Dongseog EUN ,  Young-Ho LEE ,  Joonhee LEE ,  Seok-won LEE ,  Yoocheol SHIN

IPC分类号： H01L23/498

CPC分类号： H01L23/498 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/441 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/49844 ,  H01L23/5226 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.

摘要翻译： 提供了形成由此制造的电极堆叠和三维半导体器件的方法。 该装置可以包括依次层叠在基板上以构成电极结构的电极。 每个电极可以包括从位于其上的一个电极的侧壁水平和向外突出的连接部分和具有与位于其上的电极之一的侧壁共面的对准部分。 这里，彼此垂直相邻设置的电极中的至少两个可以以这样的方式设置，使得其对准的部分具有基本上对准以彼此共面的侧壁。