Abstract:
A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The memory device includes a memory block having a plurality of banks, wherein each of the banks has a plurality of memory cells, and wherein the memory block has multiple ports. An output interface provides data on a second plurality of serial links. A cache coupled to the IO interface and to the plurality of banks, stores write data designated for a given memory cell location when the given memory cell location is currently being accessed, thereby avoiding a collision. Memory device includes one or more memory access controllers (MACs) coupled to the memory block and one or more arithmetic logic units (ALUs) coupled to the MACs. The ALUs perform one or more operations on data prior to the data being transmitted out of the IC via the IO, such as read/modify/write or statistics or traffic management functions, thereby reducing congestion on the serial links and offloading appropriate operations from the host to the memory device.
Abstract:
A composting apparatus is disclosed which comprises a container (10) formed from a plurality of segments (12a, 12b and 12c). An aerator (20, 521) is located in the container for receiving air from the exterior of the container and distributing the air into the composting mass within the container. The apparatus has a base (501) which includes a leachate chamber (454) for collecting liquid that strains from the composting mass during composting. An anti-compaction member (99, 527) is provided for preventing compost from compacting and blocking the aerator (20, 521), and a plug (570) provides addition or alternative air supply to the container (10).
Abstract:
The present invention features a sleeve valve comprising an elongate body having an outer surface and including a lumen for receiving a fluid and an associated fluid pressure therein and for defining a flow path of the fluid; at least one fluid flow port formed through the outer surface that is in fluid connection with the lumen; and a sleeve slidably disposed about the outer surface of the body and configured to displace across the fluid flow port to precisely regulate fluid emission through the fluid flow port. The sleeve and elongate body are operably related in a manner so as to provide some degree of fluid force compensation, such that the forces necessary to displace the sleeve across the fluid flow port are substantially unaffected by the fluid pressures acting within the body and at the fluid flow port. In other words, the fluid pressures do not substantially contribute to the resistance in the sleeve during actuation.
Abstract:
An apparatus and method for extracting energy from an internal combustion engine. The internal combustion engine includes a chamber having a primary piston and a secondary piston with a combustion portion of the chamber situated adjacently between the primary piston and secondary piston. The secondary piston includes a substantially lesser mass than that of the primary piston. The chamber includes at least one fluid port for supplying fuel to the combustion portion and an out-take port for releasing combustive exhaust. The chamber includes a controller for controlling the combustion therein at selected cycles of the primary piston. With this arrangement, the secondary piston is configured to draw a portion of energy from combustion controlled by the controller in the chamber. Such portion of energy is provided with a rapid response to an energy transferring portion interconnected to the secondary piston, which in turn, transfers and/or converts the energy for acting on a load or external application.
Abstract:
An integrated apparatus is disclosed that can directly connect to a portable digital video camera and can record uncompressed video and audio data, along with associated metadata, in the field and elsewhere. Most preferably, the integrated apparatus includes a removable, recordable, reusable digital magazine that may be mounted. Most preferably, the integrated apparatus also supports a variety of input and output formats, and the apparatus may be easily connected to other computing systems, either directly or through network connections, wired or wireless. The digital magazine can be mounted in a variety of docking stations and can be directly connected to a network, allowing the video and audio data to be easily stored and transferred.
Abstract:
An engine 20 has an oiling system including a pump (46) that delivers oil under nominal engine lubrication pressure to lubricate moving surfaces of the engine mechanism (42). The system also has first and second control passages (30, 32) to effect engine compression ratio change by operating connecting rod length change mechanisms (26A, 26B, 26C). Selectively operated hydraulic control devices cause pressure in the first passage to be greater than pressure in the second passage to effect an increase in engine compression ratio and pressure in the second passage to be greater than pressure in the first passage to effect a decrease in engine compression ratio. Multiple embodiments of the invention are disclosed.
Abstract:
A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
Abstract:
A floating-point unit of a computer includes a floating-point computation it, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
Abstract:
An online auction system comprises a host system. The host system comprises at least one processor capable of executing processor executable code, at least one non-transient memory capable of communicating with the at least one processor and storing processor executable code comprising a first rank associated with a first user and a second rank associated with a second user. The processor executable code when executed by the at least one processor, causes the at least one processor to access the first rank and second rank, schedule a first auction having a first rank range and a second auction having a second rank range, and present the first auction having the first rank range to the first user and the second auction having the second rank range to the second user. The first rank of the first user falls within the first rank range and the second rank of the second user falls within the second rank range. A method for scheduling online auctions comprises accessing, by a host system comprising at least one processor, processor executable code stored on a non-transient memory. The processor executable code comprises a first rank associated with a first user and a second rank associated with a second user. The host system schedules, by the at least one processor, a first auction having a first rank range and a second auction having a second rank range. The host system presents the first auction having the first rank range to the first user and the second auction having the second rank range to the second user. The first rank of the first user is identified by the first rank range and the second rank of the second user is identified by the second rank range.