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    Method for producing a plurality of chips and a chip produced accordingly
    1.
    发明授权
    Method for producing a plurality of chips and a chip produced accordingly 有权
    用于生产多个芯片的方法和相应地制造的芯片

    公开(公告)号：US08405210B2

    公开(公告)日：2013-03-26

    申请号：US12677068

    申请日：2008-07-24

    Applicant: Torsten Kramer ,  Matthias Boehringer ,  Stefan Pinter ,  Hubert Benzel ,  Matthias Illing ,  Frieder Haag ,  Simon Ambruster

    Inventor： Torsten Kramer ,  Matthias Boehringer ,  Stefan Pinter ,  Hubert Benzel ,  Matthias Illing ,  Frieder Haag ,  Simon Ambruster

    IPC: H01L23/498

    CPC classification number: H01L21/78 ,  B81C1/00896 ,  B81C2201/053

    Abstract: A production method for chips, in which as many method steps as possible are carried out in the wafer composite, that is, in parallel for a plurality of chips disposed on a wafer. This is a method for producing a plurality of chips whose functionality is implemented on the basis of the surface layer of a substrate. In this method, the surface layer is patterned and at least one cavity is produced below the surface layer, so that the individual chip regions are connected to each other and/or to the rest of the substrate by suspension webs only, and/or so that the individual chip regions are connected to the substrate layer below the cavity via supporting elements in the region of the cavity. The suspension webs and/or supporting elements are cut when the chips are separated. The patterned and undercut surface layer of the substrate is embedded in a plastic mass before the chips are separated.

    Abstract translation: 一种芯片的制造方法，其中在晶片复合体中进行尽可能多的方法步骤，即对于设置在晶片上的多个芯片并行。 这是用于制造多个芯片的方法，其功能是基于基板的表面层来实现的。 在该方法中，对表面层进行图案化，并且在表面层下方产生至少一个空腔，使得单独的芯片区域仅通过悬挂网彼此连接和/或连接到基板的其余部分，和/或 单个芯片区域通过腔体区域中的支撑元件连接到腔体下方的衬底层。 当碎片分离时，悬挂网和/或支撑元件被切割。 在芯片分离之前，将衬底的图案和底切表面层嵌入塑料块中。

    METHOD FOR PRODUCING A COMPONENT, AND SENSOR ELEMENT
    3.
    发明申请
    METHOD FOR PRODUCING A COMPONENT, AND SENSOR ELEMENT 有权
    生产组件和传感器元件的方法

    公开(公告)号：US20100164027A1

    公开(公告)日：2010-07-01

    申请号：US12522693

    申请日：2007-11-28

    Applicant: Torsten Kramer ,  Kathrin Knese ,  Hubert Benzel ,  Gregor Schuermann ,  Simon Armbruster ,  Christoph Schelling

    Inventor： Torsten Kramer ,  Kathrin Knese ,  Hubert Benzel ,  Gregor Schuermann ,  Simon Armbruster ,  Christoph Schelling

    IPC: H01L29/84 ,  H01L21/306

    CPC classification number: B81C1/00182 ,  B81B2201/0264 ,  B81B2207/015 ,  B81C2201/0115 ,  G01L19/0038

    Abstract: A method for producing a component having at least one diaphragm formed in the upper surface of the component, which diaphragm spans a cavity, and having at least one access opening to the cavity from the back side of the component, at least one first diaphragm layer and the cavity being produced in a monolithic semiconductor substrate from the upper surface of the component, and the access opening being produced in a temporally limited etching step from the back side of the substrate. The access opening is placed in a region in which the substrate material comes up to the first diaphragm layer. The etching process for producing the access opening includes at least one anisotropic etching step and at least one isotropic etching step, in the anisotropic etching step, an etching channel from the back side of the substrate being produced, which terminates beneath the first diaphragm layer in the vicinity of the cavity, and at least the end region of this etching channel being expanded in the isotropic etching step until the etching channel is connected to the cavity.

    Abstract translation: 一种用于制造具有形成在所述部件的上表面中的至少一个光阑的部件的方法，所述至少一个光阑形成在所述部件的上表面中，所述光阑跨越空腔，并且具有至少一个从所述部件的后侧到所述腔的进入开口，至少一个第一隔膜层 并且所述空腔从所述部件的上表面在单片半导体衬底中产生，并且所述存取开口在时间上受限制的蚀刻步骤中从所述衬底的背面制造。 进入口放置在基板材料到达第一隔膜层的区域中。 用于制造进出口的蚀刻工艺包括至少一个各向异性蚀刻步骤和至少一个各向同性蚀刻步骤，在各向异性蚀刻步骤中，从所述基板的背面制造蚀刻通道，其终止于第一隔膜层下方 该腔的附近，并且至少该蚀刻通道的端部区域在各向同性蚀刻步骤中扩展，直到蚀刻通道连接到空腔。

    Method for manufacturing a micromechanical chip and a component having a chip of this type
    4.
    发明申请
    Method for manufacturing a micromechanical chip and a component having a chip of this type 有权
    用于制造微机械芯片的方法和具有这种类型的芯片的部件

    公开(公告)号：US20100084722A1

    公开(公告)日：2010-04-08

    申请号：US12584148

    申请日：2009-08-31

    Applicant: Torsten KRAMER ,  Christoph SCHELLING ,  Christina LEINENBACH

    Inventor： Torsten KRAMER ,  Christoph SCHELLING ,  Christina LEINENBACH

    IPC: H01L29/84 ,  H01L21/98

    CPC classification number: B81C1/00095 ,  B81B2207/07 ,  B81C1/00626

    Abstract: In a method for manufacturing a micromechanical chip, a sacrificial layer and an epitaxy layer are initially applied to a semiconductor substrate to produce a layer stack. An opening is subsequently introduced into the epitaxy layer from the front side of the layer stack. In order to electrically insulate the subsequent filling of the opening using a conductive contact layer from the material of the epitaxy layer, the walls of the opening are provided with an insulating layer. For removing the sacrificial layer and thus for producing the chip, separation trenches are subsequently etched through the epitaxy layer to the sacrificial layer also from the front side of the layer stack, which separation trenches also delimit the lateral extension of the chip.

    Abstract translation: 在制造微机械芯片的方法中，牺牲层和外延层最初被施加到半导体衬底以产生层叠。 随后从层叠体的前侧将开口引入外延层。 为了利用来自外延层的材料的导电接触层来电绝缘开口的后续填充，开口的壁设置有绝缘层。 为了去除牺牲层并因此用于制造芯片，随后通过外延层将分离沟槽从层叠体的前侧蚀刻到牺牲层，该分离沟槽也限定了芯片的横向延伸。

    Data carrier having reset means for interrupting the processing
    5.
    发明授权
    Data carrier having reset means for interrupting the processing 有权
    数据载体具有用于中断处理的复位装置

    公开(公告)号：US06655599B2

    公开(公告)日：2003-12-02

    申请号：US09847220

    申请日：2001-05-02

    Applicant: Peter Thueringer ,  Klaus Ully ,  Peter Kompan ,  Markus Feuser ,  Torsten Kramer

    Inventor： Peter Thueringer ,  Klaus Ully ,  Peter Kompan ,  Markus Feuser ,  Torsten Kramer

    IPC: G06K1906

    CPC classification number: G06K19/0723

    Abstract: A data carrier (4) for the contactless communication of communication information (KD) with a transmitting/receiving station (1) includes receiving circuit (7) for receiving an HF signal (HF) containing the communication information (KD) from the transmitting/receiving station (1), and processing circuit (10) for processing the received communication information (KD), and supply voltage generating circuit (13) for rectifying the received HF signal (HF) and for energizing the processing circuit (10) with a supply voltage (UV), and reset circuit (14) for resetting, when the supply voltage (UV) decreases below a reset voltage value (UR), the processing performed by the processing circuit (10), the reset circuit (14) now being adapted to interrupt the processing of the communication information (KD) by the processing circuit (10) at least partially when the supply voltage (UV) decreases below an interruption voltage value (UU), the interruption voltage value (UU) being greater than the reset voltage value (UR).

    Abstract translation: 用于通信信息（KD）与发送/接收站（1）的非接触式通信的数据载体（4）包括接收电路（7），用于从发送/接收站（1）接收包含通信信息（KD）的HF信号（HF） 接收站（1）和用于处理所接收的通信信息（KD）的处理电路（10），以及用于整流所接收的HF信号（HF）的电源电压生成电路（13），以及用于使处理电路 电源电压（UV）和复位电路（14），当电源电压（UV）降低到复位电压值（UR）以下时，由处理电路（10），复位电路（14）执行的处理 适于在电源电压（UV）降低到中断电压值（UU）以下时至少部分地中断处理电路（10）对通信信息（KD）的处理，中断电压值（UU）大于 有 电压值（UR）。

    Method for producing a component, and sensor element
    6.
    发明授权
    Method for producing a component, and sensor element 有权
    用于制造组件和传感器元件的方法

    公开(公告)号：US08530261B2

    公开(公告)日：2013-09-10

    申请号：US12522693

    申请日：2007-11-28

    Applicant: Torsten Kramer ,  Kathrin Knese ,  Hubert Benzel ,  Gregor Schuermann ,  Simon Armbruster ,  Christoph Schelling

    Inventor： Torsten Kramer ,  Kathrin Knese ,  Hubert Benzel ,  Gregor Schuermann ,  Simon Armbruster ,  Christoph Schelling

    IPC: H01L21/00

    CPC classification number: B81C1/00182 ,  B81B2201/0264 ,  B81B2207/015 ,  B81C2201/0115 ,  G01L19/0038

    Abstract: A method for producing a component having at least one diaphragm formed in the upper surface of the component, which diaphragm spans a cavity, and having at least one access opening to the cavity from the back side of the component, at least one first diaphragm layer and the cavity being produced in a monolithic semiconductor substrate from the upper surface of the component, and the access opening being produced in a temporally limited etching step from the back side of the substrate. The access opening is placed in a region in which the substrate material comes up to the first diaphragm layer. The etching process for producing the access opening includes at least one anisotropic etching step and at least one isotropic etching step, in the anisotropic etching step, an etching channel from the back side of the substrate being produced, which terminates beneath the first diaphragm layer in the vicinity of the cavity, and at least the end region of this etching channel being expanded in the isotropic etching step until the etching channel is connected to the cavity.

    Abstract translation: 一种用于制造具有形成在所述部件的上表面中的至少一个光阑的部件的方法，所述至少一个光阑形成在所述部件的上表面中，所述光阑跨越空腔，并且具有至少一个从所述部件的后侧到所述腔的进入开口，至少一个第一隔膜层 并且所述空腔从所述部件的上表面在单片半导体衬底中产生，并且所述存取开口在时间上受限制的蚀刻步骤中从所述衬底的背面制造。 进入口放置在基板材料到达第一隔膜层的区域中。 用于制造进出口的蚀刻工艺包括至少一个各向异性蚀刻步骤和至少一个各向同性蚀刻步骤，在各向异性蚀刻步骤中，从所述基板的背面制造蚀刻通道，其终止在第一隔膜层下方 该腔的附近，并且至少该蚀刻通道的端部区域在各向同性蚀刻步骤中扩展，直到蚀刻通道连接到空腔。

    Method for manufacturing a micromechanical diaphragm structure having access from the rear of the substrate
    7.
    发明授权
    Method for manufacturing a micromechanical diaphragm structure having access from the rear of the substrate 有权
    用于制造从衬底的后部进入的微机械膜结构的方法

    公开(公告)号：US08519494B2

    公开(公告)日：2013-08-27

    申请号：US12737037

    申请日：2009-04-21

    Applicant: Torsten Kramer ,  Marcus Ahles ,  Armin Grundmann ,  Kathrin Knese ,  Hubert Benzel ,  Gregor Schuermann ,  Simon Armbruster

    Inventor： Torsten Kramer ,  Marcus Ahles ,  Armin Grundmann ,  Kathrin Knese ,  Hubert Benzel ,  Gregor Schuermann ,  Simon Armbruster

    IPC: G01P15/08

    CPC classification number: B81C1/00158 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81C2201/0115 ,  B81C2201/0136 ,  G01L9/0042

    Abstract: A method for manufacturing a micromechanical diaphragm structure having access from the rear of the substrate includes: n-doping at least one contiguous lattice-type area of a p-doped silicon substrate surface; porously etching a substrate area beneath the n-doped lattice structure; producing a cavity in this substrate area beneath the n-doped lattice structure; growing a first monocrystalline silicon epitaxial layer on the n-doped lattice structure; at least one opening in the n-doped lattice structure being dimensioned in such a way that it is not closed by the growing first epitaxial layer but instead forms an access opening to the cavity; an oxide layer being created on the cavity wall; a rear access to the cavity being created, the oxide layer on the cavity wall acting as an etch stop layer; and the oxide layer being removed in the area of the cavity.

    Abstract translation: 用于制造从衬底的后部进入的微机械膜结构的方法包括：n掺杂p掺杂硅衬底表面的至少一个连续的格子型区域; 在n掺杂的晶格结构下面蚀刻衬底区域; 在该n型掺杂晶格结构下面的该衬底区域中产生空腔; 在n掺杂晶格结构上生长第一单晶硅外延层; n掺杂晶格结构中的至少一个开口的尺寸设计成使得其不被生长的第一外延层闭合​​，而是形成到腔的通路口; 在空腔壁上形成氧化物层; 产生到空腔的后部通路，空腔壁上的氧化层用作蚀刻停止层; 并且在空腔的区域中去除氧化物层。

    Microcontroller and addressing method
    8.
    发明申请
    Microcontroller and addressing method 审中-公开
    微控制器和寻址方法

    公开(公告)号：US20060271762A1

    公开(公告)日：2006-11-30

    申请号：US10560572

    申请日：2004-06-04

    Applicant: Torsten Kramer

    Inventor： Torsten Kramer

    IPC: G06F12/00

    CPC classification number: G06F9/342 ,  G06F12/0623

    Abstract: In order to provide a microcontroller and an addressing method which are distinguished by a lower storage requirement and a higher execution speed than previously known when addressing N-bit address spaces, the address length N of the N-bit address word being greater than the address length of a standard set of instruction or of equivalents of other sets of instructions of the microcontroller, it is provided that the microcontroller (10) has at least one status bit (12) by means of which a writing and/or reading of N-bit address words by at least one standard instruction of the microcontroller (10) can be forced, and the at least one status bit (12) of a microcontroller (10) is set and as a a result a writing and/or reading of N-bit address words by means of at least one standard instruction of the microcontroller (10) is forced.

    Abstract translation: 为了提供一个微控制器和寻址方法，它们通过比寻址N位地址空间时先前已知的更低的存储要求和更高的执行速度来区分，N位地址字的地址长度N大于地址 微控制器的标准指令集或其他指令集的等效指令的长度，微控制器（10）具有至少一个状态位（12），通过该状态位的写入和/或读取， 可以强制微控制器（10）的至少一个标准指令的位地址字，并且设置微控制器（10）的至少一个状态位（12），并且作为结果写入和/或读取N- 通过微控制器（10）的至少一个标准指令来强制位地址字。

    Data carrier
    9.
    发明授权
    Data carrier 有权
    数据载体

    公开(公告)号：US06827278B1

    公开(公告)日：2004-12-07

    申请号：US09555306

    申请日：2000-10-06

    Applicant: Volker Timm ,  Ralf Malzahn ,  Wolfgang Eber ,  Dominik Berger ,  Jozef Laurentius Wilhelmus Kessels ,  Torsten Kramer

    Inventor： Volker Timm ,  Ralf Malzahn ,  Wolfgang Eber ,  Dominik Berger ,  Jozef Laurentius Wilhelmus Kessels ,  Torsten Kramer

    IPC: G06K1906

    CPC classification number: G06K19/07769 ,  G06K19/07 ,  G06K19/0701 ,  G06K19/073

    Abstract: A data carrier is disclosed. The data carrier includes a data processing unit and at least one contactless interface via which the data processing unit can be coupled to a read/write apparatus in order to exchange data signals and to take up electrical energy for the operation of the data processing unit; the data processing unit is constructed at least mainly while using at least substantially asynchronously operating logic components (asynchronous logic). The data carrier according to the invention, such as a chip card, makes optimum use of the energy applied thereto and is at the same time protected against the tapping of the signal processing steps to be executed therein.

    Abstract translation: 公开了数据载体。 数据载体包括数据处理单元和至少一个非接触式接口，通过该接口，数据处理单元可耦合到读/写设备，以便交换数据信号并占用用于数据处理单元操作的电能; 数据处理单元至少主要构造在使用至少基本上异步操作的逻辑组件（异步逻辑）的同时。 根据本发明的数据载体，例如芯片卡，可以最佳地利用施加到其上的能量，同时可以防止在其中执行的信号处理步骤的窃听。

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