摘要:
A latch based memory device includes a plurality of latches and a method of testing the latch based memory device that includes serially connecting the latches with each other so as to form a shift register chain. A bit sequence is input into the shift register chain to shift the bit sequence through the shift register chain. A bit sequence is outputted and shifted through the shift register chain, and the input bit sequence is compared with the output sequence to evaluate the functionality of the latches in a first test phase and to test the remaining structures of the latch based memory device in a second test phase by using, e.g., a conventional scan test approach.
摘要:
Circuit for calculating a logic combination of two encrypted input operands recieves first and second dual-rail signals comprising data values in a calculation cycle and precharge values in a precharge cycle, and receives a dual-rail encryption signal comprising encryption values in the calculation cycle and precharge values in the precharge cycle, and outputs a dual-rail result signal comprising encrypted result values in the calculation cycle and precharge values in the precharge cycle. The data and encrypted result values are encrypted with the encryption values of the dual-rail encryption signal according to an encryption rule. A logic circuit determines the encrypted result values according to the logic combination from the data and encryption values, and outputs the encrypted result values in the calculation cycle. A precharge circuit impresses precharge values when precharge values are sensed at a single input, or stops impressing the precharge values only when the first and second dual-rail signals comprise data values and the dual-rail encryption signal comprises encryption values.
摘要:
A method of fabricating an integrated circuit including arranging a plurality of cells to form a desired floor plan of the integrated circuit, wherein each cell comprises at least one transistor, forming a plurality of circuit constituents from the plurality of cells of the floor plan, wherein each circuit constituent comprises at least one cell and belongs to one of a plurality circuit constituent types, and applying mechanical stress to channel regions of the at least one transistor of each cell based on the circuit constituent type of the circuit constituent to which the cell belongs.
摘要:
A circuit arrangement for supplying configuration data in an FPGA device includes a plurality of output flip flops allocated to respective configurable logic cells of the FGPGA device. Each output flip flop comprises at least one data input and one data output and a data input of a first output flip flop of the plurality of output flip flops is switchably connected to a data output of a second output flip flop of the plurality of output flip flops for forming a shift register by means of a switching device integrated in the FPGA device.
摘要:
The invention relates to an adder for adding at least four bits of the same significance w, said adder having a first number of inputs for receiving the bits of the same significance w that are to be added and a number of outputs, the bits to be added being applied to the inputs in presorted form, and the adder adding the bits while taking account of the presorting. The invention also provides an adding device for adding at least four bits of equal significance and a corresponding method.
摘要:
A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle, a second input for receiving a second dual rail signal having data values of the second input in the calculation cycle and precharge values in the precharge cycle, and an output for outputting a third dual rail signal having result values in the calculation cycle and precharge values in the precharge cycle. Furthermore, the circuit has a logic circuit for determining the result values according to the logical combination from the data values of the first input and the second input and for outputting the result values in the calculation cycle at the output, and a precharge circuit designed to impress precharge values in the output already when precharge values are detected at a single input, or designed to terminate impressing the precharge values only when the first dual rail signal and the second dual rail signal have data values.
摘要:
A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle, a second input for receiving a second dual rail signal having data values of the second input in the calculation cycle and precharge values in the precharge cycle, and an output for outputting a third dual rail signal having result values in the calculation cycle and precharge values in the precharge cycle. Furthermore, the circuit has a logic circuit for determining the result values according to the logical combination from the data values of the first input and the second input and for outputting the result values in the calculation cycle at the output, and a precharge circuit designed to impress precharge values in the output already when precharge values are detected at a single input, or designed to terminate impressing the precharge values only when the first dual rail signal and the second dual rail signal have data values.
摘要:
A carry-ripple adder having inputs for supplying three input bits of equal significance 2n that are to be summed and two carry bits of equal significance 2n+1 that are also to be summed. A calculated sum bit of significance 2n and two calculated carry bits of equal significance 2n+1 which are higher than the significance 2n of the sum bit are provided at outputs. A final carry-ripple stage VMA may be used even after a reduction to three bits.
摘要翻译:具有输入的输入纹波加法器,其具有用于提供要求和的三个等号有效值的输入比特和两个相等重要性的两个进位比特2 n + 1,也是 被总结。 计算出的有效值的和位2< n>和两个具有相同重要性的计算的进位位2< n + 1< / 2>其高于 在输出端提供和位。 即使在减少到三位之后,也可以使用最终的进位纹波级VMA。
摘要:
One embodiment provides a content addressable memory cell having a first memory cell which is electrically connected to a comparator unit. The comparator unit is constructed from at least eight transistors, at least four transistors being arranged in a first circuit part and at least four transistors being arranged in a second circuit part and each of the circuit parts having at least two circuit branches.
摘要:
A logic circuit for calculating an encrypted dual-rail result operand from encrypted dual-rail input operands according to a combination rule includes inputs for receiving the input operands and an output for outputting the encrypted result operand. Each operand may comprise a first logic state or a second logic state. The logic circuit comprises a first logic stage connected between the inputs and an intermediate node and a second logic stage connected between the intermediate node and the output. The logic stages are formed to calculate the first or second logic state of the encrypted result operand from the input operands according to the combination rule and to maintain or change exactly once the logic state of the encrypted result operand, independently of an order of arrival of the encrypted input operands, depending on the combination rule, in order to impress the calculated first logic state or second logic state on the output.