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    Processor and method for processing instructions using at least one processing pipeline
    1.
    发明授权
    Processor and method for processing instructions using at least one processing pipeline 有权
    用于使用至少一个处理流水线处理指令的处理器和方法

    公开(公告)号：US09213547B2

    公开(公告)日：2015-12-15

    申请号：US13826553

    申请日：2013-03-14

    Applicant: ARM LIMITED

    Inventor： Ian Michael Caulfield ,  Peter Richard Greenhalgh ,  Max John Batley

    IPC: G06F9/30 ,  G06F9/00

    CPC classification number: G06F9/30079 ,  G06F9/3836 ,  G06F9/3875 ,  G06F9/3885

    Abstract: A processor has a processing pipeline with first, second and third stages. An instruction at the first stage takes fewer cycles to reach the second stage then the third stage. The second and third stages each have a duplicated processing resource. For a pending instruction which requires the duplicated resource and can be processed using the duplicated resource at either of the second and third stages, the first stage determines whether a required operand would be available when the pending instruction would reach the second stage. If the operand would be available, then the pending instruction is processed using the duplicated resource at the second stage, while if the operand would not be available in time then the instruction is processed using the duplicated resource in the third pipeline stage. This technique helps to reduce delays caused by data dependency hazards.

    Abstract translation: 处理器具有第一，第二和第三阶段的处理流水线。 第一阶段的指令需要更少的周期才能到达第二阶段，然后到第三阶段。 第二和第三阶段各有一个重复的处理资源。 对于要求复制的资源并且可以使用第二级和第三级中的任一级的重复资源来处理的等待指令，第一级确定当待命指令将到达第二级时所需的操作数是否可用。 如果操作数可用，则在第二阶段使用重复的资源处理挂起的指令，而如果操作数在时间上不可用，则使用第三流水线阶段中的重复资源处理指令。 这种技术有助于减少数据依赖性危害造成的延误。

    Apparatus and method for avoiding conflicting entries in a storage structure
    3.
    发明授权
    Apparatus and method for avoiding conflicting entries in a storage structure 有权

    公开(公告)号：US10083126B2

    公开(公告)日：2018-09-25

    申请号：US15370570

    申请日：2016-12-06

    Applicant: ARM Limited

    Inventor： Richard F Bryant ,  Max John Batley ,  Lilian Atieno Hutchins ,  Sujat Jamil

    IPC: G06F12/12 ,  G06F12/10 ,  G06F12/1036

    CPC classification number: G06F12/12 ,  G06F12/1027 ,  G06F12/1036 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/652 ,  G06F2212/681 ,  G06F2212/683 ,  G06F2212/684

    Abstract: An apparatus and method are provided for avoiding conflicting entries in a storage structure. The apparatus comprises a storage structure having a plurality of entries for storing data, and allocation circuitry, responsive to a trigger event for allocating new data into the storage structure, to determine a victim entry into which the new data is to be stored, and to allocate the new data into the victim entry upon determining that the new data is available. Conflict detection circuitry is used to detect when the new data will conflict with data stored in one or more entries of the storage structure, and to cause the data in said one or more entries to be invalidated. The conflict detection circuitry is arranged to perform, prior to a portion of the new data required for conflict detection being available, at least one initial stage detection operation to determine, based on an available portion of the new data, candidate entries whose data may conflict with the new data. A record of the candidate entries in then maintained, and, once the portion of the new data required for conflict detection is available, the conflict detection circuitry then performs a final stage detection operation to determine whether any of the candidate entries do contain data that conflicts with the new data. Any entries identified by the final stage detection operation as containing data that conflicts with the new data are then invalidated. This provides a particularly efficient mechanism for avoiding conflicting entries in a storage structure.

    Mode switching in dependence upon a number of active threads
    4.
    发明授权
    Mode switching in dependence upon a number of active threads 有权

    公开(公告)号：US10705587B2

    公开(公告)日：2020-07-07

    申请号：US15133329

    申请日：2016-04-20

    Applicant: ARM LIMITED

    Inventor： Peter Richard Greenhalgh ,  Simon John Craske ,  Ian Michael Caulfield ,  Max John Batley ,  Allan John Skillman ,  Antony John Penton

    IPC: G06F9/38 ,  G06F1/3206 ,  G06F1/3287 ,  G06F9/30 ,  G06F1/3234 ,  G06F1/3237

    Abstract: Apparatus for processing data is provided with fetch circuitry for fetching program instructions for execution from one or more active threads of instructions having respective program counter values. Pipeline circuitry has a first operating mode and a second operating mode. Mode switching circuitry switches the pipeline circuitry, between the first operating mode and the second operating mode in dependence upon a number of active threads of program instructions having program instructions available to be executed. The first operating mode has a lower average energy consumption per instruction executed than the second operating mode and the second operating mode has a higher average rate of instruction execution for a single thread than the first operating mode. The first operating mode may utilise a barrel processing pipeline to perform interleaved multiple thread processing. The second operating mode may utilise an out-of-order processing pipeline for performing out-of-order processing.

    Data storage
    5.
    发明授权
    Data storage 有权

    公开(公告)号：US10310735B2

    公开(公告)日：2019-06-04

    申请号：US15440254

    申请日：2017-02-23

    Applicant: ARM Limited

    Inventor： Cédric Denis Robert Airaud ,  Max John Batley ,  Ian Michael Caulfield ,  Thomas Edward Roberts

    IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G06F12/06 ,  G06F12/02 ,  G06F12/0893

    Abstract: Data storage apparatus comprises detection circuitry configured to detect a match between a multi-bit reference memory address and a test address, the test address being a combination of a multi-bit base address and a multi-bit address offset, the detection circuitry comprising: a comparator configured to compare, as a first comparison, a first subset of bits of the reference memory address with a combination of the corresponding first subset of bits of the base address and the corresponding first subset of bits of the address offset; the comparator being configured to compare, as a second comparison, a second, different subset of bits of the reference memory address with the corresponding second subset of bits of the base address; a detector configured to detect the match between the reference memory address and the test address when both of the first comparison and the second comparison detect a respective match; and control circuitry configured to control operation of the data storage apparatus in dependence upon the reference memory address when a match is detected by the detector.

    Arbitration of requests requiring a variable number of resources
    6.
    发明授权
    Arbitration of requests requiring a variable number of resources 有权

    公开(公告)号：US10521368B2

    公开(公告)日：2019-12-31

    申请号：US14757577

    申请日：2015-12-24

    Applicant: ARM LIMITED

    Inventor： Max John Batley ,  Ian Michael Caulfield ,  Chris Abernathy

    IPC: G06F13/16 ,  G06F12/128 ,  G06F12/12

    Abstract: Arbitration circuitry is provided for arbitrating between requests awaiting servicing. The requests require variable numbers of resources and the arbitration circuitry permits the request to be serviced in a different order to the order in which they were received. Checking circuitry prevents a given request other than a oldest request from being serviced when a number of available resources is less than a threshold number of resources. The threshold number is varied based on the number of resources required for at least one other request awaiting servicing.

    Determining a predicted behaviour for processing of instructions
    7.
    发明授权
    Determining a predicted behaviour for processing of instructions 有权

    公开(公告)号：US10402203B2

    公开(公告)日：2019-09-03

    申请号：US15578477

    申请日：2016-03-31

    Applicant: ARM LIMITED

    Inventor： Max John Batley ,  Simon John Craske ,  Ian Michael Caulfield ,  Peter Richard Greenhalgh ,  Allan John Skillman ,  Antony John Penton

    IPC: G06F9/30 ,  G06F9/38

    Abstract: An apparatus comprises prediction circuitry (40, 100, 80) for determining, based on current prediction policy information (43, 82, 104), a predicted behavior to be used for processing instructions. The current prediction policy information is updated based on an outcome of processing of instructions. A storage structure (50) stores at least one entry identifying previous prediction policy information (60) for a corresponding block of instructions. In response to an instruction from a block having a corresponding entry in the storage structure (50) which identifies the previous prediction policy information (60), the current prediction policy information (43, 82, 104) can be reset based on the previous prediction policy information 60 identified in the corresponding entry of the storage structure (50).

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