公开(公告)号：US20190155159A1

公开(公告)日：2019-05-23

申请号：US16094119

申请日：2017-04-07

Applicant: ASM IP HOLDING B.V. ,  IMEC VZW

Inventor： Werner Knaepen ,  Jan Willem Maes ,  Maarten Stokhof ,  Roel Gronheid ,  Hari Pathangi Sriraman

IPC: G03F7/16

Abstract: A method of forming a directed self-assembled (DSA) layer on a substrate by: providing a substrate; applying a layer comprising a self-assembly material on the substrate; and annealing of the self-assembly material of the layer to form a directed self-assembled layer by providing a controlled temperature and gas environment around the substrate. The controlled gas environment comprises molecules comprising an oxygen element with a partial pressure between 10-2000 Pa.

公开(公告)号：US10551741B2

公开(公告)日：2020-02-04

申请号：US16094119

申请日：2017-04-07

Applicant: ASM IP HOLDING B.V. ,  IMEC VZW

Inventor： Werner Knaepen ,  Jan Willem Maes ,  Maarten Stokhof ,  Roel Gronheid ,  Hari Pathangi Sriraman

IPC: G03F7/16 ,  H01L21/027 ,  H01L21/67 ,  H01L21/768 ,  H01L51/00 ,  H01L21/469 ,  H01L21/31 ,  B05D3/04 ,  B05D3/02

Abstract: A method of forming a directed self-assembled (DSA) layer on a substrate by: providing a substrate; applying a layer comprising a self-assembly material on the substrate; and annealing of the self-assembly material of the layer to form a directed self-assembled layer by providing a controlled temperature and gas environment around the substrate. The controlled gas environment comprises molecules comprising an oxygen element with a partial pressure between 10-2000 Pa.

公开(公告)号：US20240339359A1

公开(公告)日：2024-10-10

申请号：US18626758

申请日：2024-04-04

Applicant: ASM IP Holding B.V.

Inventor： René Henricus Jozef Vervuurt ,  Timothee Blanquart ,  Jihee Jeon ,  YongMin Yoo ,  Andrey Sokolov ,  Maarten Stokhof ,  Steven Van Aerde ,  Dieter Pierreux ,  Hussein Mehdi

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76879 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/02274

Abstract: The present disclosure relates to method and apparatuses for filling a gap on a substrate. The method comprises providing a substrate, which comprises at least one gap into a reaction chamber, depositing a silicon containing first layer onto the substrate; subjecting the first layer to a phosphorous containing compound to form a flowable intermediate material, which at least partially fills the at least one gap on the substrate; and forming a solid material comprising silicon.

公开(公告)号：US10453685B2

公开(公告)日：2019-10-22

申请号：US15476752

申请日：2017-03-31

Applicant: ASM IP Holding B.V.

Inventor： Kelly Houben ,  Steven R. A. Van Aerde ,  Maarten Stokhof ,  Bert Jongbloed ,  Dieter Pierreux ,  Werner Knaepen

IPC: H01L21/311 ,  H01L21/033

Abstract: The invention relates to a method of forming a semiconductor device by patterning a substrate by providing an amorphous silicon layer on the substrate and forming a hard mask layer on the amorphous silicon layer. The amorphous silicon layer is provided with an anti-crystallization dopant to keep the layer amorphous at increased temperatures (relative to not providing the anti-crystallization dopant). The hard mask layer may comprise silicon and nitrogen.

公开(公告)号：US10460932B2

公开(公告)日：2019-10-29

申请号：US15476702

申请日：2017-03-31

Applicant: ASM IP Holding B.V.

Inventor： Steven R. A. Van Aerde ,  Kelly Houben ,  Maarten Stokhof ,  Bert Jongbloed ,  Dieter Pierreux

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/28 ,  H01L29/78

Abstract: Amorphous silicon-filled gaps may be formed having no or a low occurrence of voids in the amorphous silicon fill, while maintaining a smooth exposed silicon surface. A gap in a substrate may be filled with amorphous silicon by heating the substrate to a deposition temperature between 300 and 500° C. and providing a feed gas that comprises a first silicon reactant to deposit an amorphous silicon film into the gap with an hydrogen concentration between 0.1 and 10 at. %. The deposited silicon film may subsequently be annealed. After the anneal, any voids may be reduced in size and this reduction in size may occur to such an extent that the voids may be eliminated.

公开(公告)号：US20180286679A1

公开(公告)日：2018-10-04

申请号：US15476752

申请日：2017-03-31

Applicant: ASM IP Holding B.V.

Inventor： Kelly Houben ,  Steven R.A. Van Aerde ,  Maarten Stokhof ,  Bert Jongbloed ,  Dieter Pierreux ,  Werner Knaepen

IPC: H01L21/033

CPC classification number: H01L21/0337

Abstract: The invention relates to a method of forming a semiconductor device by patterning a substrate by providing an amorphous silicon layer on the substrate and forming a hard mask layer on the amorphous silicon layer. The amorphous silicon layer is provided with an anti-crystallization dopant to keep the layer amorphous at increased temperatures (relative to not providing the anti-crystallization dopant). The hard mask layer may comprise silicon and nitrogen.

公开(公告)号：US20180286672A1

公开(公告)日：2018-10-04

申请号：US15476702

申请日：2017-03-31

Applicant: ASM IP Holding B.V.

Inventor： Steven R.A. Van Aerde ,  Kelly Houben ,  Maarten Stokhof ,  Bert Jongbloed ,  Dieter Pierreux

IPC: H01L21/02 ,  H01L21/324 ,  H01L21/306

Abstract: Amorphous silicon-filled gaps may be formed having no or a low occurrence of voids in the amorphous silicon fill, while maintaining a smooth exposed silicon surface. A gap in a substrate may be filled with amorphous silicon by heating the substrate to a deposition temperature between 300 and 500° C. and providing a feed gas that comprises a first silicon reactant to deposit an amorphous silicon film into the gap with an hydrogen concentration between 0.1 and 10 at. %. The deposited silicon film may subsequently be annealed. After the anneal, any voids may be reduced in size and this reduction in size may occur to such an extent that the voids may be eliminated.