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公开(公告)号：US20180174583A1
公开(公告)日：2018-06-21
申请号：US15706178
申请日：2017-09-15
Applicant: Avnera Corporation
Inventor： Xudong Zhao , Alexander C. Stange , Shawn O'Connor , Ali Hadiashar
CPC classification number: G10L15/22 , G10L25/78 , G10L25/84 , G10L2015/088 , G10L2025/783 , H03M3/458
Abstract: A system for detecting and capturing voice commands, the system comprising a voice-activity detector (VAD) configured to receive a VAD-received digital-audio signal; determine the amplitude of the VAD-received digital-audio signal; compare the amplitude of the VAD-received digital-audio signal to a first threshold and to a second threshold; withhold a VAD interrupt signal when the amplitude of the VAD-received digital-audio signal does not exceed the first threshold or the second threshold; generate the VAD interrupt signal when the amplitude of the VAD-received digital-audio signal exceeds the first threshold and the second threshold; and perform spectral analysis of the VAD-received digital-audio signal when the amplitude of the VAD-received digital-audio signal is between the first threshold and the second threshold.
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公开(公告)号：US20180054297A1
公开(公告)日：2018-02-22
申请号：US15799473
申请日：2017-10-31
Applicant: AVNERA CORPORATION
Inventor： Samuel J. Peters, II , Eric P. Etheridge , Victor Lee Hansen , Alexander C. Stange
CPC classification number: H04L7/033 , G06F13/4295 , H04L7/0029 , H04L7/02
Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digital oversampler; and an AND gate configured to pass the “toothless” clock signal to the sample rate converter responsive to a determination that an output of the sample counter is greater than zero.
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公开(公告)号：US20170222793A1
公开(公告)日：2017-08-03
申请号：US15484408
申请日：2017-04-11
Applicant: AVNERA CORPORATION
Inventor： Samuel J. Peters, II , Eric P. Etheridge , Victor Lee Hansen , Alexander C. Stange
CPC classification number: H04L7/033 , G06F13/4295 , H04L7/0029 , H04L7/02
Abstract: A method can include a digital oversampler oversampling an input data stream, a rate generator selecting a frequency that is not less than an expected frequency of the input data stream, a rate generator clock of the rate generator outputting a clock signal that has the selected frequency, determining whether a sample receiver has received at least one sample of the input data stream from the digital oversampler, and, responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler, incrementing a sample counter by each received sample. The method can also include a sample rate converter accumulating samples from the sample receiver at the rate of a “toothless” clock signal, determining whether an output of the sample counter is greater than zero, and, responsive to a determination that the output of the sample counter is greater than zero, an AND gate passing the “toothless” clock signal to the sample rate converter.
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公开(公告)号：US09621336B1
公开(公告)日：2017-04-11
申请号：US14471324
申请日：2014-08-28
Applicant: Avnera Corporation
Inventor： Samuel J. Peters, II , Eric P. Etheridge , Victor Lee Hansen , Alexander C. Stange
IPC: H04L7/033
CPC classification number: H04L7/033 , G06F13/4295 , H04L7/0029 , H04L7/02
Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated from the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.
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公开(公告)号：US10476659B2
公开(公告)日：2019-11-12
申请号：US16049474
申请日：2018-07-30
Applicant: AVNERA CORPORATION
Inventor： Samuel J. Peters, II , Eric P. Etheridge , Victor Lee Hansen , Alexander C. Stange
Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digital oversampler; and an AND gate configured to pass the “toothless” clock signal to the sample rate converter responsive to a determination that an output of the sample counter is greater than zero.
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Patent Agency Ranking
公开(公告)号：US10425053B2
公开(公告)日：2019-09-24
申请号：US15858101
申请日：2017-12-29
Applicant: Avnera Corporation
Inventor： Garry N. Link , Eric King , Xudong Zhao , Wai Lee , Alexander C. Stange , Amit Kumar
Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.
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公开(公告)号：US20190207575A1
公开(公告)日：2019-07-04
申请号：US16295987
申请日：2019-03-07
Applicant: Avnera Corporation
Inventor： Garry N. Link , Eric King , Xudong Zhao , Wai Lee , Alexander C. Stange , Amit Kumar
CPC classification number: H03G3/004 , H03F1/025 , H03F1/305 , H03F3/187 , H03F2200/507 , H03F2200/511 , H03G3/32
Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.
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公开(公告)号：US10230343B2
公开(公告)日：2019-03-12
申请号：US15858101
申请日：2017-12-29
Applicant: Avnera Corporation
Inventor： Garry N. Link , Eric King , Xudong Zhao , Wai Lee , Alexander C. Stange , Amit Kumar
Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.
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公开(公告)号：US10403279B2
公开(公告)日：2019-09-03
申请号：US15706178
申请日：2017-09-15
Applicant: Avnera Corporation
Inventor： Xudong Zhao , Alexander C. Stange , Shawn O'Connor , Ali Hadiashar
Abstract: A system for detecting and capturing voice commands, the system comprising a voice-activity detector (VAD) configured to receive a VAD-received digital-audio signal; determine the amplitude of the VAD-received digital-audio signal; compare the amplitude of the VAD-received digital-audio signal to a first threshold and to a second threshold; withhold a VAD interrupt signal when the amplitude of the VAD-received digital-audio signal does not exceed the first threshold or the second threshold; generate the VAD interrupt signal when the amplitude of the VAD-received digital-audio signal exceeds the first threshold and the second threshold; and perform spectral analysis of the VAD-received digital-audio signal when the amplitude of the VAD-received digital-audio signal is between the first threshold and the second threshold.
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公开(公告)号：US10038548B2
公开(公告)日：2018-07-31
申请号：US15799473
申请日：2017-10-31
Applicant: AVNERA CORPORATION
Inventor： Samuel J. Peters, II , Eric P. Etheridge , Victor Lee Hansen , Alexander C. Stange
CPC classification number: H04L7/033 , G06F13/4295 , H04L7/0029 , H04L7/02
Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digital oversampler; and an AND gate configured to pass the “toothless” clock signal to the sample rate converter responsive to a determination that an output of the sample counter is greater than zero.
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