公开(公告)号：US10552339B2

公开(公告)日：2020-02-04

申请号：US16005882

申请日：2018-06-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Arkaprava Basu ,  Joseph L. Greathouse

IPC: G06F12/10 ,  G06F12/1027 ,  G06F9/48

Abstract: An operating system (OS) of a processing system having a plurality of processor cores determines a cost associated with different mechanisms for performing a translation lookaside buffer (TLB) shootdown in response to, for example, a virtual address being remapped to a new physical address, and selects a TLB shootdown mechanism to purge outdated or invalid address translations from the TLB based on the determined cost. In some embodiments, the OS selects an inter-processor interrupt (IPI) as the TLB shootdown mechanism if the cost associated with sending an IPI is less than a threshold cost. In some embodiments, the OS compares the cost of using an IPI as the TLB shootdown mechanism versus the cost of sending a hardware broadcast to all processor cores of the processing system as the shootdown mechanism and selects the shootdown mechanism having the lower cost.

公开(公告)号：US10282292B2

公开(公告)日：2019-05-07

申请号：US15295025

申请日：2016-10-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Andreas Prodromou ,  Mitesh R. Meswani ,  Arkaprava Basu ,  Nuwan S. Jayasena ,  Gabriel H. Loh

IPC: G06F12/0811 ,  G06F9/50

Abstract: Cluster manager functional blocks perform operations for migrating pages in portions in corresponding migration clusters. During operation, each cluster manager keeps an access record that includes information indicating accesses of pages in the portions in the corresponding migration cluster. Based on the access record and one or more migration policies, each cluster manager migrates pages between the portions in the corresponding migration cluster.

公开(公告)号：US20180088858A1

公开(公告)日：2018-03-29

申请号：US15274777

申请日：2016-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Mitesh R. Meswani ,  Dibakar Gope ,  Sooraj Puthoor

IPC: G06F3/06 ,  G06F12/0804

CPC classification number: G06F3/0647 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0685 ,  G06F12/0246

Abstract: A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.

公开(公告)号：US20170337136A1

公开(公告)日：2017-11-23

申请号：US15162464

申请日：2016-05-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Bradford M. Beckmann ,  Shuai Che ,  Sooraj Puthoor

IPC: G06F12/1009 ,  G06F12/0815 ,  G06F12/14

CPC classification number: G06F12/1009 ,  G06F12/0817 ,  G06F12/0837 ,  G06F12/1027 ,  G06F12/1483 ,  G06F2212/1024 ,  G06F2212/1052 ,  G06F2212/621 ,  G06F2212/657

Abstract: The described embodiments include a computing device with two or more types of processors and a memory that is shared between the two or more types of processors. The computing device performs operations for handling cache coherency between the two or more types of processors. During operation, the computing device sets a cache coherency indicator in metadata in a page table entry in a page table, the page table entry information about a page of data that is stored in the memory. The computing device then uses the cache coherency indicator to determine operations to be performed when accessing data in the page of data in the memory. For example, the computing device can use the coherency indicator to determine whether a coherency operation is to be performed when a processor of a given type accesses data in the page of data in the memory.

公开(公告)号：US20160371082A1

公开(公告)日：2016-12-22

申请号：US14746601

申请日：2015-06-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Dmitri Yudanov ,  Sergey Blagodurov ,  Arkaprava Basu ,  Sooraj Puthoor ,  Joseph L. Greathouse

IPC: G06F9/30

CPC classification number: G06F9/461 ,  G06F9/3013 ,  G06F9/3851

Abstract: A processing device includes a first memory that includes a context buffer. The processing device also includes a processor core to execute threads based on context information stored in registers of the processor core and a memory controller to selectively move a subset of the context information between the context buffer and the registers based on one or more latencies of the threads.

Abstract translation: 处理装置包括包括上下文缓冲器的第一存储器。 处理设备还包括处理器核心，用于基于存储在处理器核心的寄存器中的上下文信息来执行线程，以及存储器控制器，用于基于上下文缓冲器和寄存器的一个或多个延迟来选择性地移动上下文信息的子集 线程。

公开(公告)号：US11573724B2

公开(公告)日：2023-02-07

申请号：US16432391

申请日：2019-06-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Mitesh R. Meswani ,  Dibakar Gope ,  Sooraj Puthoor

IPC: G06F3/06 ,  G06F12/02

Abstract: A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.

公开(公告)号：US20220269535A1

公开(公告)日：2022-08-25

申请号：US17684214

申请日：2022-03-01

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Joseph Lee Greathouse

IPC: G06F9/48 ,  G06F9/46

Abstract: Systems, apparatuses, and methods for enforcing processor quality of service guarantees when servicing system service requests (SSRs) are disclosed. A system includes a first processor executing an operating system and a second processor executing an application which generates SSRs for the first processor to service. The first processor monitors the number of cycles spent servicing SSRs over a previous time interval, and if this number of cycles is above a threshold, the first processor starts delaying the servicing of subsequent SSRs. In one implementation, if the previous delay was non-zero, the first processor increases the delay used in the servicing of subsequent SSRs. If the number of cycles is less than or equal to the threshold, then the first processor services SSRs without delay. As the delay is increased, the second processor begins to stall and its SSR generation rate falls, reducing the load on the first processor.

公开(公告)号：US10324650B2

公开(公告)日：2019-06-18

申请号：US15274777

申请日：2016-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Mitesh R. Meswani ,  Dibakar Gope ,  Sooraj Puthoor

IPC: G06F3/06 ,  G06F12/02

Abstract: A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.

公开(公告)号：US10261916B2

公开(公告)日：2019-04-16

申请号：US15361335

申请日：2016-11-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Amro Awad ,  Sergey Blagodurov ,  Arkaprava Basu ,  Mark H. Oskin ,  Gabriel H. Loh ,  Andrew G. Kegel ,  David S. Christie ,  Kevin J. McGrath

IPC: G06F12/10 ,  G06F12/1036 ,  G06F12/1009 ,  G06F12/1027

Abstract: The described embodiments include a computing device with two or more translation lookaside buffers (TLB). During operation, the computing device updates an entry in the TLB based on a virtual address to physical address translation and metadata from a page table entry that were acquired during a page table walk. The computing device then computes, based on a lease length expression, a lease length for the entry in the TLB. Next, the computing device sets, for the entry in the TLB, a lease value to the lease length, wherein the lease value represents a time until a lease for the entry in the TLB expires, wherein the entry in the TLB is invalid when the associated lease has expired. The computing device then uses the lease value to control operations that are allowed to be performed using information from the entry in the TLB.

公开(公告)号：US20170277634A1

公开(公告)日：2017-09-28

申请号：US15081379

申请日：2016-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Mark H. Oskin ,  Gabriel H. Loh ,  Andrew G. Kegel ,  David S. Christie ,  Kevin J. McGrath

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/0811 ,  G06F2212/1024 ,  G06F2212/683 ,  G06F2212/684

Abstract: The described embodiments include a computing device with two or more translation lookaside buffers (TLB) that performs operations for handling entries in the TLBs. During operation, the computing device maintains lease values for entries in the TLBs, the lease values representing times until leases for the entries expire, wherein a given entry in the TLB is invalid when the associated lease has expired. The computing device uses the lease value to control operations that are allowed to be performed using information from the entries in the TLBs. In addition, the computing device maintains, in a page table, longest lease values for page table entries indicating when corresponding longest leases for entries in TLBs expire. The longest lease values are used to determine when and if a TLB shootdown is to be performed.