公开(公告)号：US20130282784A1

公开(公告)日：2013-10-24

申请号：US13921316

申请日：2013-06-19

Applicant: Advanced Micro Devices,Inc.

Inventor： David S. Oliver ,  Debjit Das Sarma ,  Scott Hilker

IPC: G06F7/483

CPC classification number: G06F7/483 ,  G06F7/49942 ,  G06F7/5443

Abstract: A device and methods are disclosed for communicating an unrounded result from one arithmetic calculation for use in a second, subsequent calculation. For example, an unrounded result of a first calculation can be forwarded to provide a multiplier, a multiplicand or an addend operand for the subsequent operation. The operand can be forwarded to the input of the same fused multiply addition module (FMAM) that supplied the result, or to another FMAM, and do so without regard to the precision of the forwarded operand, the precision of the subsequent operation, or the native precision of the FMAM.

Abstract translation: 公开了一种用于传送来自一个算术计算的未包围结果以用于第二次后续计算的装置和方法。 例如，可以转发第一次计算的未包围的结果以提供用于后续操作的乘法器，被乘数或加数操作数。 操作数可以转发给提供结果的相同的融合乘法加法模块（FMAM）的输入，或转发给另一个FMAM，并且不考虑转发操作数的精度，后续操作的精度，或者 FMAM的本机精度。

公开(公告)号：US10768937B2

公开(公告)日：2020-09-08

申请号：US16046949

申请日：2018-07-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Marius Evers ,  David A. Kaplan ,  Debjit Das Sarma

IPC: G06F9/30 ,  G06F9/38

Abstract: Overhead associated with verifying function return addresses to protect against security exploits is reduced by taking advantage of branch prediction mechanisms for predicting return addresses. More specifically, returning from a function includes popping a return address from a data stack. Well-known security exploits overwrite the return address on the data stack to hijack control flow. In some processors, a separate data structure referred to as a control stack is used to verify the data stack. When a return instruction is executed, the processor issues an exception if the return addresses on the control stack and the data stack are not identical. This overhead can be avoided by taking advantage of the return address stack, which is a data structure used by the branch predictor to predict return addresses. In most situations, if this prediction is correct, the above check does not need to occur, thus reducing the associated overhead.

公开(公告)号：US10127044B2

公开(公告)日：2018-11-13

申请号：US14522831

申请日：2014-10-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Douglas Williams ,  Sahil Arora ,  Nikhil Gupta ,  Wei-Yu Chen ,  Debjit Das Sarma ,  Marius Evers

IPC: G06F9/38 ,  G06F9/30

Abstract: A processor, a device, and a non-transitory computer readable medium for performing branch prediction in a processor are presented. The processor includes a front end unit. The front end unit includes a level 1 branch target buffer (BTB), a BTB index predictor (BIP), and a level 1 hash perceptron (HP). The BTB is configured to predict a target address. The BIP is configured to generate a prediction based on a program counter and a global history, wherein the prediction includes a speculative partial target address, a global history value, a global history shift value, and a way prediction. The HP is configured to predict whether a branch instruction is taken or not taken.

公开(公告)号：US20150121050A1

公开(公告)日：2015-04-30

申请号：US14522831

申请日：2014-10-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Douglas Williams ,  Sahil Arora ,  Nikhil Gupta ,  Wei-Yu Chen ,  Debjit Das Sarma ,  Marius Evers

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30058 ,  G06F9/3848

Abstract: A processor, a device, and a non-transitory computer readable medium for performing branch prediction in a processor are presented. The processor includes a front end unit. The front end unit includes a level 1 branch target buffer (BTB), a BTB index predictor (BIP), and a level 1 hash perceptron (HP). The BTB is configured to predict a target address. The BIP is configured to generate a prediction based on a program counter and a global history, wherein the prediction includes a speculative partial target address, a global history value, a global history shift value, and a way prediction. The HP is configured to predict whether a branch instruction is taken or not taken.

Abstract translation: 提出了一种用于在处理器中执行分支预测的处理器，设备和非暂时性计算机可读介质。 处理器包括前端单元。 前端单元包括1级分支目标缓冲器（BTB），BTB索引预测器（BIP）和1级散列感知器（HP）。 BTB被配置为预测目标地址。 BIP被配置为基于程序计数器和全局历史生成预测，其中预测包括推测性部分目标地址，全局历史值，全局历史偏移值和路径预测。 HP配置为预测是否采用分支指令。

公开(公告)号：US09582286B2

公开(公告)日：2017-02-28

申请号：US13673350

申请日：2012-11-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Ganesh Venkataramanan ,  Debjit Das Sarma ,  Betty A. McDaniel ,  Gregory W. Smaus ,  Francesco Spadini

IPC: G06F9/30 ,  G06F9/44 ,  G06F9/38

CPC classification number: G06F9/3857 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/384

Abstract: A processor includes a physical register file having physical registers and an execution unit to perform an arithmetic operation to generate a result mapped to a physical register, wherein the processor delays a write of the result to the physical register file until the result is qualified as valid. A method includes mapping the same physical register both to store load data of a load-execute operation and to subsequently store a result of an arithmetic operation of the load-execute operation, and writing the load data into the physical register. The method further includes, in a first clock cycle, executing the arithmetic operation to generate the result, and, in a second clock cycle, providing the result as a source operand for a dependent operation. The method includes, in a third clock cycle, enabling a write of the result to the physical register file responsive to the result qualifying as valid.

Abstract translation: 处理器包括具有物理寄存器的物理寄存器文件和用于执行算术运算以产生映射到物理寄存器的结果的执行单元，其中处理器将结果的写入延迟到物理寄存器堆，直到结果合格为有效 。 一种方法包括将相同的物理寄存器映射到存储加载执行操作的负载数据，并随后存储加载执行操作的算术运算的结果，并将加载数据写入物理寄存器。 该方法还包括在第一时钟周期中执行算术运算以产生结果，并且在第二时钟周期中，将结果提供为依赖操作的源操作数。 该方法包括在第三时钟周期中，使结果符合有效的结果写入物理寄存器文件。

公开(公告)号：US09317250B2

公开(公告)日：2016-04-19

申请号：US13674220

申请日：2012-11-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Kelvin D. Goveas ,  Debjit Das Sarma ,  Scott A. Hilker ,  Hanbing Liu

IPC: G06F7/483 ,  G06F7/499 ,  G06F7/544

CPC classification number: G06F7/483 ,  G06F7/49936 ,  G06F7/5443

Abstract: The present application provides a method and apparatus for supporting denormal numbers in a floating point multiply-add unit (FMAC). One embodiment of the FMAC is configurable to add a product of first and second operands to a third operand. This embodiment of the FMAC is configurable to determine a minimum exponent shift for a sum of the product and the third operand by subtracting a minimum normal exponent from a product exponent of the product. This embodiment of the FMAC is also configurable to cause bits representing the sum to be left shifted by the minimum exponent shift if a third exponent of the third operand is less than or equal to the product exponent and the minimum exponent shift is less than or equal to a predicted left shift for the sum.

Abstract translation: 本申请提供了一种用于支持浮点乘法单元（FMAC）中的反常数的方法和装置。 FMAC的一个实施例可配置为将第一和第二操作数的乘积添加到第三操作数。 FMAC的该实施例可配置为通过从乘积的乘积指数减去最小正态指数来确定乘积和第三操作数之和的最小指数偏移。 如果FMAC的这个实施例如果第三操作数的第三指数小于或等于乘积指数并且最小指数移位小于或等于，则可配置为使表示和的位移动移位最小指数移位 到总和的预测左移。

公开(公告)号：US20200034144A1

公开(公告)日：2020-01-30

申请号：US16046949

申请日：2018-07-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Marius Evers ,  David A. Kaplan ,  Debjit Das Sarma

IPC: G06F9/30 ,  G06F9/38

Abstract: Overhead associated with verifying function return addresses to protect against security exploits is reduced by taking advantage of branch prediction mechanisms for predicting return addresses. More specifically, returning from a function includes popping a return address from a data stack. Well-known security exploits overwrite the return address on the data stack to hijack control flow. In some processors, a separate data structure referred to as a control stack is used to verify the data stack. When a return instruction is executed, the processor issues an exception if the return addresses on the control stack and the data stack are not identical. This overhead can be avoided by taking advantage of the return address stack, which is a data structure used by the branch predictor to predict return addresses. In most situations, if this prediction is correct, the above check does not need to occur, thus reducing the associated overhead.

公开(公告)号：US20140136819A1

公开(公告)日：2014-05-15

申请号：US13673350

申请日：2012-11-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ganesh Venkataramanan ,  Debjit Das Sarma ,  Betty A. McDaniel ,  Gregory W. Smaus ,  Francesco Spadini

IPC: G06F9/30

CPC classification number: G06F9/3857 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/384

Abstract: A processor includes a physical register file having physical registers and an execution unit to perform an arithmetic operation to generate a result mapped to a physical register, wherein the processor delays a write of the result to the physical register file until the result is qualified as valid. A method includes mapping the same physical register both to store load data of a load-execute operation and to subsequently store a result of an arithmetic operation of the load-execute operation, and writing the load data into the physical register. The method further includes, in a first clock cycle, executing the arithmetic operation to generate the result, and, in a second clock cycle, providing the result as a source operand for a dependent operation. The method includes, in a third clock cycle, enabling a write of the result to the physical register file responsive to the result qualifying as valid.

Abstract translation: 处理器包括具有物理寄存器的物理寄存器文件和用于执行算术运算以产生映射到物理寄存器的结果的执行单元，其中处理器将结果的写入延迟到物理寄存器堆，直到结果合格为有效 。 一种方法包括将相同的物理寄存器映射到存储加载执行操作的负载数据，并随后存储加载执行操作的算术运算的结果，并将加载数据写入物理寄存器。 该方法还包括在第一时钟周期中执行算术运算以产生结果，并且在第二时钟周期中，将结果提供为依赖操作的源操作数。 该方法包括在第三时钟周期中，使结果符合有效的结果写入物理寄存器文件。