公开(公告)号：US10593391B2

公开(公告)日：2020-03-17

申请号：US16038738

申请日：2018-07-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Liang Zhao ,  YuBin Yao

IPC: G11C11/406 ,  G06F13/18 ,  G06F13/16 ,  G11C11/4076

Abstract: In one form, a memory controller includes a command queue, an arbiter, a refresh logic circuit, and a final arbiter. The command queue receives and stores memory access requests for a memory. The arbiter selectively picks accesses from the command queue according to a first type of accesses and a second type of accesses. The first type of accesses and the second type of accesses correspond to different page statuses of corresponding memory accesses in the memory. The refresh logic circuit generates a refresh command to a bank of the memory and provides a priority indicator with the refresh command whose value is set according to a number of pending refreshes. The final arbiter selectively orders the refresh command with respect to memory access requests of the first type accesses and the second type accesses based on the priority indicator.

公开(公告)号：US20230418772A1

公开(公告)日：2023-12-28

申请号：US17849117

申请日：2022-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Hideki Kanayama ,  YuBin Yao

IPC: G06F13/16

CPC classification number: G06F13/1689 ,  G06F13/1642 ,  G06F13/1621

Abstract: A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request selectively for the first pseudo channel and the second pseudo channel.

公开(公告)号：US20250061071A1

公开(公告)日：2025-02-20

申请号：US18909595

申请日：2024-10-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Hideki Kanayama ,  YuBin Yao

IPC: G06F13/16

Abstract: A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request selectively for the first pseudo channel and the second pseudo channel.

公开(公告)号：US11742043B2

公开(公告)日：2023-08-29

申请号：US17506746

申请日：2021-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： YuBin Yao ,  Eric M. Scott ,  TieFeng Liu

IPC: G11C29/00 ,  G11C29/02 ,  G06F3/06 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C29/028 ,  G06F3/0673 ,  G11C7/1066 ,  G11C7/222 ,  G11C29/023

Abstract: A method for performing read training of a memory channel includes writing a data pattern to a memory using a data bus having a predetermined number of bit lanes. An edge of a read data eye is determined individually for each bit lane by reading the data pattern over the data bus using a read bust cycle having a predetermined length, grouping data received on each bit lane over the read burst cycle to form a bit lane data group, and comparing the bit lane data group to corresponding expected data of the data pattern for each bit lane, logging a phase of each bit lane on which said edge is found, and repeating the reading, grouping, comparing, and logging until the edge is found for all of the bit lanes.

公开(公告)号：US11675659B2

公开(公告)日：2023-06-13

申请号：US15375076

申请日：2016-12-09

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： James R. Magro ,  Ruihua Peng ,  Anthony Asaro ,  Kedarnath Balakrishnan ,  Scott P. Murphy ,  YuBin Yao

IPC: G06F11/10 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F11/1016 ,  G06F11/10 ,  G06F13/1626 ,  G06F13/4022

Abstract: In one form, a memory controller includes a command queue, an arbiter, and a replay queue. The command queue receives and stores memory access requests. The arbiter is coupled to the command queue for providing a sequence of memory commands to a memory channel. The replay queue stores the sequence of memory commands to the memory channel, and continues to store memory access commands that have not yet received responses from the memory channel. When a response indicates a completion of a corresponding memory command without any error, the replay queue removes the corresponding memory command without taking further action. When a response indicates a completion of the corresponding memory command with an error, the replay queue replays at least the corresponding memory command. In another form, a data processing system includes the memory controller, a memory accessing agent, and a memory system to which the memory controller is coupled.

公开(公告)号：US20230132306A1

公开(公告)日：2023-04-27

申请号：US17506746

申请日：2021-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： YuBin Yao ,  Eric M. Scott ,  TieFeng Liu

IPC: G06F3/06

Abstract: A method for performing read training of a memory channel includes writing a data pattern to a memory using a data bus having a predetermined number of bit lanes. An edge of a read data eye is determined individually for each bit lane by reading the data pattern over the data bus using a read bust cycle having a predetermined length, grouping data received on each bit lane over the read burst cycle to form a bit lane data group, and comparing the bit lane data group to corresponding expected data of the data pattern for each bit lane, logging a phase of each bit lane on which said edge is found, and repeating the reading, grouping, comparing, and logging until the edge is found for all of the bit lanes.

公开(公告)号：US12117945B2

公开(公告)日：2024-10-15

申请号：US17849117

申请日：2022-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Hideki Kanayama ,  YuBin Yao

IPC: G06F13/16

CPC classification number: G06F13/1689 ,  G06F13/1621 ,  G06F13/1642

Abstract: A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request selectively for the first pseudo channel and the second pseudo channel.

公开(公告)号：US20200020384A1

公开(公告)日：2020-01-16

申请号：US16038738

申请日：2018-07-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Liang Zhao ,  YuBin Yao

IPC: G11C11/406 ,  G11C11/4076 ,  G06F13/16 ,  G06F13/18

Abstract: In one form, a memory controller includes a command queue, an arbiter, a refresh logic circuit, and a final arbiter. The command queue receives and stores memory access requests for a memory. The arbiter selectively picks accesses from the command queue according to a first type of accesses and a second type of accesses. The first type of accesses and the second type of accesses correspond to different page statuses of corresponding memory accesses in the memory. The refresh logic circuit generates a refresh command to a bank of the memory and provides a priority indicator with the refresh command whose value is set according to a number of pending refreshes. The final arbiter selectively orders the refresh command with respect to memory access requests of the first type accesses and the second type accesses based on the priority indicator.

公开(公告)号：US20180018221A1

公开(公告)日：2018-01-18

申请号：US15375076

申请日：2016-12-09

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Ruihua Peng ,  Anthony Asaro ,  Kedarnath Balakrishnan ,  Scott P. Murphy ,  YuBin Yao

IPC: G06F11/10 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F11/1016 ,  G06F11/10 ,  G06F13/1626 ,  G06F13/4022

Abstract: In one form, a memory controller includes a command queue, an arbiter, and a replay queue. The command queue receives and stores memory access requests. The arbiter is coupled to the command queue for providing a sequence of memory commands to a memory channel. The replay queue stores the sequence of memory commands to the memory channel, and continues to store memory access commands that have not yet received responses from the memory channel. When a response indicates a completion of a corresponding memory command without any error, the replay queue removes the corresponding memory command without taking further action. When a response indicates a completion of the corresponding memory command with an error, the replay queue replays at least the corresponding memory command. In another form, a data processing system includes the memory controller, a memory accessing agent, and a memory system to which the memory controller is coupled.