公开(公告)号：US09887167B1

公开(公告)日：2018-02-06

申请号：US15269787

申请日：2016-09-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih Cheng Lee ,  Hsing Kuo Tien ,  Li Chuan Tsai

IPC: H01L23/34 ,  H01L23/00 ,  H01L23/538 ,  H01L23/367 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L23/3677 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/24227 ,  H01L2224/24247 ,  H01L2224/2518 ,  H01L2224/29191 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/3511

Abstract: A package structure includes a carrier defining a cavity in which a die is disposed. A dielectric material fills the cavity around the die. A first conductive layer is disposed over a first surface of the carrier. A first dielectric layer is disposed over an active surface of the die, the first conductive layer and the first surface of the carrier. A first conductive pattern is disposed over the first dielectric layer, and is electrically connected to the first conductive layer and to the active surface of the die. A second dielectric layer is disposed over the second surface of the carrier and defines a hole having a wall aligned with a sidewall of the cavity. A second conductive layer is disposed over the second dielectric layer. A third conductive layer is disposed on the sidewall of the cavity and the wall of the second dielectric layer.

公开(公告)号：US10381296B2

公开(公告)日：2019-08-13

申请号：US15699810

申请日：2017-09-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li Chuan Tsai ,  Chih-Cheng Lee

IPC: H01L23/498 ,  H01L21/48 ,  H05K3/34 ,  H05K1/11 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31

Abstract: At least some embodiments of the present disclosure relate to a substrate for packaging a semiconductor device. The substrate includes a first dielectric layer having a first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a conductive post. The first patterned conductive layer includes a first conductive pad and a second conductive pad. The conductive post is disposed on the first conductive pad. The conductive post includes a first portion and a second portion. The first portion and the second portion of the conductive post are exposed by the first dielectric layer. The first portion of the conductive post has a first width corresponding to a top line width of the first portion and the second portion of the conductive post has a width. The width of the second portion of the conductive post is greater than the first width of the first portion of the conductive post.

公开(公告)号：US10748843B2

公开(公告)日：2020-08-18

申请号：US15356407

申请日：2016-11-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li Chuan Tsai ,  Po-Shu Peng ,  Cheng-Lin Ho ,  Chih Cheng Lee

IPC: H05K1/18 ,  H01L23/498 ,  H05K3/46 ,  H01L21/48

Abstract: A semiconductor substrate includes a multi-layered structure, a component and a first conductive via. The multi-layered structure includes a plurality of dielectric layers and a plurality of patterned conductive layers. A topmost patterned conductive layer of the patterned conductive layers is embedded in a topmost dielectric layer of the dielectric layers. The component is embedded in the multi-layered structure. The first conductive via is electrically connected to the component and one of the patterned conductive layers. At least one of the patterned conductive layers is located at a depth spanning between a top surface of the passive layer and a bottom surface of the component

公开(公告)号：US10446515B2

公开(公告)日：2019-10-15

申请号：US15450598

申请日：2017-03-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li Chuan Tsai ,  Chih-Cheng Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor substrate includes a first dielectric layer, a first patterned conductive layer disposed in the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and a first bump pad disposed in the second dielectric layer. The first bump pad is electrically connected to the first patterned conductive layer, and the first bump pad has a curved surface surrounded by the second dielectric layer.

公开(公告)号：US09984898B2

公开(公告)日：2018-05-29

申请号：US15630847

申请日：2017-06-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li Chuan Tsai ,  Chih-Cheng Lee ,  Cheng-Lin Ho

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/498 ,  H01L24/16

Abstract: A substrate includes a dielectric layer having a first surface and a second surface opposite to the first surface, a first circuit layer and at least one second conductive element. The first circuit layer is disposed adjacent to the first surface of the dielectric layer, and includes at least one trace and at least one first conductive element connected to the trace. The first conductive element does not extend through the dielectric layer. The second conductive element extends through the dielectric layer. An area of an upper surface of the second conductive element is substantially equal to an area of an upper surface of the first conductive element.