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    Wiring structure, electronic device and method for manufacturing the same
    2.
    发明授权
    Wiring structure, electronic device and method for manufacturing the same 有权

    公开(公告)号：US11031326B2

    公开(公告)日：2021-06-08

    申请号：US16802478

    申请日：2020-02-26

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Wen Hung Huang ,  Chien-Mei Huang ,  Yan Wen Chung

    IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

    Abstract: A wiring structure includes an insulating layer and a conductive structure. The insulating layer has an upper surface and a lower surface opposite to the upper surface, and defines an opening extending through the insulating layer. The conductive structure is disposed in the opening of the insulating layer, and includes a first barrier layer and a wetting layer. The first barrier layer is disposed on a sidewall of the opening of the insulating layer, and defines a through hole extending through the first barrier layer. The wetting layer is disposed on the first barrier layer. A portion of the wetting layer is exposed from the through hole of the first barrier layer and the lower surface of the insulating layer to form a ball pad.

    Wiring structure and method for manufacturing the same
    3.
    发明授权
    Wiring structure and method for manufacturing the same 有权

    公开(公告)号：US10892213B2

    公开(公告)日：2021-01-12

    申请号：US16236207

    申请日：2018-12-28

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Wen Hung Huang ,  Li-Yu Hsieh ,  Yan Wen Chung

    IPC: H01L23/498 ,  H01L21/48 ,  H01L21/66 ,  H01L23/544 ,  H01L21/683 ,  H05K3/40 ,  H05K3/36 ,  H01L23/00

    Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, an adhesion layer and at least one outer via. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The adhesion layer is interposed between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together. The outer via extends through at least a portion of the upper conductive structure and the adhesion layer, and electrically connected to the circuit layer of the lower conductive structure.

    Semiconductor package and semiconductor process
    6.
    发明授权
    Semiconductor package and semiconductor process 有权

    公开(公告)号：US10522492B2

    公开(公告)日：2019-12-31

    申请号：US15614563

    申请日：2017-06-05

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Wen Hung Huang ,  Yan Wen Chung ,  Chien-Mei Huang

    IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L23/14 ,  H01L23/04 ,  H01L23/498 ,  H01L21/3213

    Abstract: A wiring structure includes a dielectric layer and a first patterned conductive layer on the dielectric layer. The dielectric layer has a first region and a second region. The first patterned conductive layer includes a number of fine conductive lines and a number of dummy conductive structures. The number of conductive lines include a first number of conductive lines on the first region and a second number of conductive lines on the second region, and the number of dummy conductive structures include a first number of dummy conductive structures on the second region. The first number of conductive lines occupy a first area on the first region, and the second number of conductive lines and the first number of dummy conductive structures occupy a second area on the second region. A ratio of the second area to the first area is greater than or equal to about 80%.

    Semiconductor package structure and method for manufacturing the same
    9.
    发明授权
    Semiconductor package structure and method for manufacturing the same 有权

    公开(公告)号：US10651052B2

    公开(公告)日：2020-05-12

    申请号：US15870315

    申请日：2018-01-12

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Wen Hung Huang ,  Yan Wen Chung

    IPC: H01L23/48 ,  H01L21/48 ,  H01L23/498 ,  H01L23/66 ,  H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

    Abstract: A semiconductor package structure includes a first insulating layer, a first conductive layer, a multi-layered circuit structure, a protection layer, and a semiconductor chip electrically connected to the multi-layered circuit structure. The first insulating layer defines a first through hole extending through the first insulating layer. The first conductive layer includes a conductive pad disposed in the first through hole and a trace disposed on an upper surface of the first insulating layer. The multi-layered circuit structure is disposed on an upper surface of the first conductive layer. The multi-layered circuit structure includes a bonding region disposed on the conductive pad of the first conductive layer and an extending region disposed on the trace of the first conductive layer. The protection layer covers the upper surface of the first insulating layer and the extending region of the multi-layered circuit structure, and exposes the bonding region of the multi-layered circuit structure.

    Wiring structure and semiconductor package having the same
    10.
    发明授权
    Wiring structure and semiconductor package having the same 有权

    公开(公告)号：US10468340B2

    公开(公告)日：2019-11-05

    申请号：US15625920

    申请日：2017-06-16

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Wen Hung Huang ,  Yan Wen Chung ,  Wei Chu Sun

    IPC: H01L23/498 ,  H01L23/00

    Abstract: The present disclosure relates to a wiring structure and a semiconductor package. The wiring structure comprises a first wiring pattern, a dielectric layer and a dummy structure. The first wiring pattern includes a conductive land having a width W1 and a surface area A, and a conductive trace having a width W2 and electrically connected to the conductive land, wherein ((W1*W2)/A)*100%≤ about 25%. The dielectric layer covers the first wiring pattern, and the dummy structure is adjacent to the conductive trace.

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