公开(公告)号：US20210033785A1

公开(公告)日：2021-02-04

申请号：US16528331

申请日：2019-07-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Hsuan WU ,  Yung-Hui WANG

IPC: G02B6/12 ,  G02B6/42

Abstract: An optical communication package structure includes a wiring structure, at least one via structure, a redistribution structure, at least one optical device and at least one electrical device. The wiring structure includes a main portion and a conductive structure disposed on an upper surface of the main portion. The main portion defines at least one through hole extending through the main portion. The via structure is disposed in the at least one through hole of the main portion and electrically connected to the conductive structure. The redistribution structure is disposed on a lower surface of the main portion and electrically connected to the via structure. The optical device is disposed adjacent to the upper surface of the main portion and electrically connected to the conductive structure. The electrical device is disposed on and electrically connected to the conductive structure.

公开(公告)号：US20220236480A1

公开(公告)日：2022-07-28

申请号：US17719277

申请日：2022-04-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Hsuan WU ,  Yung-Hui WANG

IPC: G02B6/12 ,  G02B6/42

Abstract: An optical communication package structure includes a wiring structure, at least one via structure, a redistribution structure, at least one optical device and at least one electrical device. The wiring structure includes a main portion and a conductive structure disposed on an upper surface of the main portion. The main portion defines at least one through hole extending through the main portion. The via structure is disposed in the at least one through hole of the main portion and electrically connected to the conductive structure. The redistribution structure is disposed on a lower surface of the main portion and electrically connected to the via structure. The optical device is disposed adjacent to the upper surface of the main portion and electrically connected to the conductive structure. The electrical device is disposed on and electrically connected to the conductive structure.

公开(公告)号：US20160118325A1

公开(公告)日：2016-04-28

申请号：US14990425

申请日：2016-01-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Hui WANG ,  Ying-Te OU

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/185 ,  H05K1/188 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/10674 ,  H05K2203/063 ,  Y10T29/4913 ,  Y10T29/49204 ,  Y10T29/49213

Abstract: An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.

Abstract translation: 嵌入式芯片基板包括第一绝缘层，芯层，芯片，第二绝缘层，第一电路层和第二电路层。 设置在第一绝缘层上的芯层具有露出第一绝缘层的一部分的开口。 芯片被粘合到由开口和第一绝缘层构成的凹槽中。 第二绝缘层设置在芯层上以覆盖芯片。 第一电路层设置在位于第一电路层和芯层之间的第一绝缘层的外侧。 第二电路层设置在位于第二电路层和芯层之间的第二绝缘层的外侧。 第一电路层电连接到电连接到芯片的第二电路层。

公开(公告)号：US20180122749A1

公开(公告)日：2018-05-03

申请号：US15340808

申请日：2016-11-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Chih LEE ,  Chin-Cheng KUO ,  Yung-Hui WANG ,  Wei-Hong LAI ,  Chung-Ting WANG ,  Hsiao-Yen LEE

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/81192

Abstract: A semiconductor wafer includes a substrate structure, a first insulation layer, a conductive layer and a second insulation layer. The substrate structure defines a via. The first insulation layer covers a surface of the substrate structure. The first insulation layer extends into the via, covers a lateral wall of the via and exposes a bottom surface at a bottom of the via. The conductive layer covers the first insulation layer and the bottom surface exposed by the first insulation layer. The second insulation layer covers the conductive layer. A warpage of the semiconductor wafer is less than 550 micrometers.