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    Device method for enhanced avalanche SOI CMOS
    1.
    发明授权
    Device method for enhanced avalanche SOI CMOS 失效
    增强型雪崩SOI CMOS器件方法

    公开(公告)号：US06249029B1

    公开(公告)日：2001-06-19

    申请号：US09320595

    申请日：1999-05-26

    申请人： Andres Bryant ,  William F. Clark ,  John J. Ellis-Monaghan ,  Edward P. Maciejewski ,  Edward J. Nowak ,  Wilbur D. Pricer ,  Minh H. Tong

    发明人： Andres Bryant ,  William F. Clark ,  John J. Ellis-Monaghan ,  Edward P. Maciejewski ,  Edward J. Nowak ,  Wilbur D. Pricer ,  Minh H. Tong

    IPC分类号： H01L2976

    CPC分类号： H01L29/7841 ,  H01L27/1203

    摘要： A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.

    摘要翻译： 用于SOI CMOS中的FET的器件设计，其被设计用于当FET导通时增强通过器件的电流的雪崩倍增，并且当FET关闭时去除体电荷。 FET具有电浮动体并且与衬底基本上电隔离。 本发明提供了将FET的浮体耦合到FET的源极的高电阻路径，使得该电阻器使得该器件能够充当用于有源开关目的的浮动体并且作为待机模式中的接地体以减少 漏电流。 高电阻路径具有至少1MΩ的电阻，并且包括通过使用分离多晶硅工艺制造的多晶硅电阻器，其中掩埋接触掩模在第一多晶硅层中打开孔，以允许第二多晶硅层 接触基板。

    Device design for enhanced avalanche SOI CMOS
    2.
    发明授权
    Device design for enhanced avalanche SOI CMOS 有权
    增强型雪崩SOI CMOS器件设计

    公开(公告)号：US5959335A

    公开(公告)日：1999-09-28

    申请号：US159307

    申请日：1998-09-23

    申请人： Andres Bryant ,  William F. Clark ,  John J. Ellis-Monaghan ,  Edward P. Maciejewski ,  Edward J. Nowak ,  Wilbur D. Pricer ,  Minh H. Tong

    发明人： Andres Bryant ,  William F. Clark ,  John J. Ellis-Monaghan ,  Edward P. Maciejewski ,  Edward J. Nowak ,  Wilbur D. Pricer ,  Minh H. Tong

    IPC分类号： H01L27/06 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC分类号： H01L29/7841 ,  H01L27/1203

    摘要： A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.

    摘要翻译： 用于SOI CMOS中的FET的器件设计，其被设计用于当FET导通时增强通过器件的电流的雪崩倍增，并且当FET关闭时去除体电荷。 FET具有电浮动体并且与衬底基本上电隔离。 本发明提供了将FET的浮体耦合到FET的源极的高电阻路径，使得该电阻器使得该器件能够充当用于有源开关目的的浮动体并且作为待机模式中的接地体以减少 漏电流。 高电阻路径具有至少1MΩ的电阻，并且包括通过使用分离多晶硅工艺制造的多晶硅电阻器，其中掩埋接触掩模在第一多晶硅层中打开孔，以允许第二多晶硅层 接触基板。

    PIXEL SENSOR CELL WITH A DUAL WORK FUNCTION GATE ELECTODE
    4.
    发明申请
    PIXEL SENSOR CELL WITH A DUAL WORK FUNCTION GATE ELECTODE 有权
    具有双功能门电极的像素传感器单元

    公开(公告)号：US20120211854A1

    公开(公告)日：2012-08-23

    申请号：US13029670

    申请日：2011-02-17

    申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

    IPC分类号： H01L31/0352 ,  G06F17/50 ,  H01L31/18

    CPC分类号： H01L27/14614

    摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage.

    摘要翻译： 像素传感器单元，制造像素传感器单元的方法以及像素传感器单元的设计结构。 像素传感器单元具有在栅极电介质上包括栅极电介质和栅电极的栅极结构。 栅极电极包括具有在栅极电介质上具有并置关系的第一和第二部分的层。 栅电极的第二部分由诸如掺杂多晶硅或金属的导体组成。 栅电极的第一部分由具有比包括第二部分的导体更高的功函的金属组成，使得栅极结构具有非对称阈值电压。

    Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure
    10.
    发明授权
    Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure 有权
    具有合并源极/漏极硅化物的鳍型场效应晶体管结构和形成结构的方法

    公开(公告)号：US07851865B2

    公开(公告)日：2010-12-14

    申请号：US11873521

    申请日：2007-10-17

    申请人： Brent A. Anderson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Edward J. Nowak

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.

    摘要翻译： 这里公开了多鳍片式场效应晶体管（即，多鳍式双栅极或三栅极场效应晶体管）的设计结构的实施例，其中多个散热片部分或完全由高导电材料 （例如，金属硅化物）。 以这种方式合并散热片使串联电阻最小化，栅极和源极/漏极区之间的寄生电容几乎不增加。 以这种方式合并半导体散热片也允许每个源极/漏极区域通过单个触点通孔接触，以及该触点通孔的更灵活的放置。