公开(公告)号：US10402326B1

公开(公告)日：2019-09-03

申请号：US15138666

申请日：2016-04-26

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Mahesh K. Reddy ,  David J. Williamson

IPC: G06F12/0815

Abstract: A system that includes circuitry to access memories in both coherent and non-coherent domains is disclosed. The circuitry may receive a command to access a memory included in the coherent domain and generate one or more commands to access a memory in the non-coherent domain dependent upon the received command. The circuitry may send the generated one or more commands to the memory in the non-coherent domain via communication bus.

公开(公告)号：US10289191B2

公开(公告)日：2019-05-14

申请号：US15866014

申请日：2018-01-09

Applicant: Apple Inc.

Inventor： David J. Williamson ,  Gerard R. Williams, III

IPC: G06F1/32 ,  G06F1/3293 ,  G06F1/3287 ,  G06F9/46 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3296

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, but may have higher minimum voltage at which it operates correctly. Another core may be implemented at a lower maximum performance, but may be optimized for efficiency and may operate correctly at a lower minimum voltage. The processor may support multiple processor states (PStates). Each PState may specify an operating point and may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core.

公开(公告)号：US20180129271A1

公开(公告)日：2018-05-10

申请号：US15866014

申请日：2018-01-09

Applicant: Apple Inc.

Inventor： David J. Williamson ,  Gerard R. Williams, III

IPC: G06F1/32 ,  G06F9/46

CPC classification number: G06F1/3293 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/461 ,  Y02B70/123 ,  Y02D10/172 ,  Y02D10/30

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, but may have higher minimum voltage at which it operates correctly. Another core may be implemented at a lower maximum performance, but may be optimized for efficiency and may operate correctly at a lower minimum voltage. The processor may support multiple processor states (PStates). Each PState may specify an operating point and may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core.

公开(公告)号：US09852084B1

公开(公告)日：2017-12-26

申请号：US15017427

申请日：2016-02-05

Applicant: Apple Inc.

Inventor： Peter G. Soderquist ,  Pradeep Kanapathipillai ,  Bernard J. Semeria ,  Joshua P. de Cesare ,  David J. Williamson ,  Gerard R. Williams, III

IPC: G06F12/14 ,  G06F12/1009

CPC classification number: G06F12/1483 ,  G06F12/1009 ,  G06F2212/1052

Abstract: Systems, apparatuses, and methods for modifying access permissions in a processor. A processor may include one or more permissions registers for managing access permissions. A first permissions register may be utilized to override access permissions embedded in the page table data. A plurality of bits from the page table data may be utilized as an index into the first permissions register for the current privilege level. An attribute field may be retrieved from the first permissions register to determine the access permissions for a given memory request. A second permissions register may also be utilized to set the upper and lower boundary of a region in physical memory where the kernel is allowed to execute. A lock register may prevent any changes from being made to the second permissions register after the second permissions register has been initially programmed.

公开(公告)号：US20210064539A1

公开(公告)日：2021-03-04

申请号：US16874997

申请日：2020-05-15

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion ,  Bernard Joseph Semeria ,  Michael J. Swift ,  Pradeep Kanapathipillai ,  David J. Williamson

IPC: G06F12/1009 ,  G06F12/1072 ,  G06F12/0873 ,  G06F12/14

Abstract: A system and method for efficiently transferring address mappings and data access permissions corresponding to the address mappings. A computing system includes at least one processor and memory for storing a page table. In response to receiving a memory access operation comprising a first address, the address translation unit is configured to identify a data access permission based on a permission index corresponding to the first address, and access data stored in a memory location of the memory identified by a second address in a manner defined by the retrieved data access permission. The address translation unit is configured to access a table to identify the data access permission, and is configured to determine the permission index and the second address based on the first address. A single permission index may correspond to different permissions for different entities within the system.

公开(公告)号：US10922232B1

公开(公告)日：2021-02-16

申请号：US16400847

申请日：2019-05-01

Applicant: Apple Inc.

Inventor： Brett S. Feero ,  David E. Kroesche ,  David J. Williamson

IPC: G06F12/08 ,  G06F12/0873 ,  G06F12/084 ,  G06F12/0888 ,  G06F12/0837

Abstract: An apparatus includes a control circuit and a cache memory with a plurality of regions. The control circuit receives a first and a second access request to access the cache memory. In response to determining that the first access request is from a particular processor core, and that the first access request is associated with a particular cache line in the cache memory, the control circuit stores the first access request in a cache access queue. In response to a determination that the second access request is received from a functional circuit, and that the second access request is associated with a range of a memory address space mapped to a subset of the plurality of regions, the control circuit stores the second access request in a memory access queue. The control circuit arbitrates access to the cache memory circuit between the first access request and the second access request.

公开(公告)号：US20180217659A1

公开(公告)日：2018-08-02

申请号：US15935274

申请日：2018-03-26

Applicant: Apple Inc.

Inventor： David J. Williamson ,  Gerard R. Williams, III ,  James N. Hardage, JR. ,  Richard F. Russo

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3293 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/5044 ,  G06F9/5094 ,  G06F2009/45579 ,  Y02D10/122 ,  Y02D10/171

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.

公开(公告)号：US09898071B2

公开(公告)日：2018-02-20

申请号：US14548872

申请日：2014-11-20

Applicant: Apple Inc.

Inventor： David J. Williamson ,  Gerard R. Williams, III

IPC: G06F1/32 ,  G06F9/46

CPC classification number: G06F1/3293 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/461 ,  Y02B70/123 ,  Y02D10/172 ,  Y02D10/30

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, but may have higher minimum voltage at which it operates correctly. Another core may be implemented at a lower maximum performance, but may be optimized for efficiency and may operate correctly at a lower minimum voltage. The processor may support multiple processor states (PStates). Each PState may specify an operating point and may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core.

公开(公告)号：US11221962B2

公开(公告)日：2022-01-11

申请号：US16874997

申请日：2020-05-15

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion ,  Bernard Joseph Semeria ,  Michael J. Swift ,  Pradeep Kanapathipillai ,  David J. Williamson

IPC: G06F12/1009 ,  G06F12/14 ,  G06F12/0873 ,  G06F12/1072

Abstract: A system and method for efficiently transferring address mappings and data access permissions corresponding to the address mappings. A computing system includes at least one processor and memory for storing a page table. In response to receiving a memory access operation comprising a first address, the address translation unit is configured to identify a data access permission based on a permission index corresponding to the first address, and access data stored in a memory location of the memory identified by a second address in a manner defined by the retrieved data access permission. The address translation unit is configured to access a table to identify the data access permission, and is configured to determine the permission index and the second address based on the first address. A single permission index may correspond to different permissions for different entities within the system.

公开(公告)号：US10007616B1

公开(公告)日：2018-06-26

申请号：US15062448

申请日：2016-03-07

Applicant: Apple Inc.

Inventor： Brett S. Feero ,  David J. Williamson ,  Jonathan J. Tyler ,  Mary D. Brown

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0831 ,  G06F12/128

CPC classification number: G06F12/0875 ,  G06F9/3802 ,  G06F9/3806 ,  G06F12/0862 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/502

Abstract: In an embodiment, an apparatus includes a cache memory and a control circuit. The control circuit may be configured to pre-fetch and store a first quantity of instruction data in response to a determination that a first pre-fetch operation request is received after a reset and prior to a first end condition. The first end condition may depend on an amount of unused storage in the cache memory. The control circuit may be further configured to pre-fetch and store a second quantity of instruction data in response to a determination that a second pre-fetch operation request is received after the first end condition. The second quantity may be less than the first quantity.