公开(公告)号：US09529533B1

公开(公告)日：2016-12-27

申请号：US15177596

申请日：2016-06-09

Applicant: Apple Inc.

Inventor： Michael A. Dreesen ,  Naveen Javarappa ,  Ajay Kumar Bhatia ,  Greg M. Hess

IPC: G11C5/14 ,  G06F3/06 ,  G06F1/32 ,  G06F1/26 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/418 ,  G06F1/3275 ,  G06F1/3296 ,  G11C5/14 ,  G11C11/417 ,  G11C11/419 ,  Y02D10/14 ,  Y02D10/172

Abstract: An apparatus for modifying a voltage level of a memory array power supply is disclosed. A first column may include a first plurality of data storage cells coupled to a first local power supply signal and a second column may include a second plurality of data storage cells coupled to a second local power supply signal. A first switch may be configured to selectively coupled the first local power supply signal to either a first power signal or a second power supply signal dependent upon a value of a first selection signal, and a second switch may be configured to selectively couple the second local power supply signal to either the first power supply signal or the second power supply signal dependent upon a value of a second selection signal.

Abstract translation: 公开了一种用于修改存储器阵列电源的电压电平的装置。 第一列可以包括耦合到第一本地电源信号的第一多个数据存储单元，并且第二列可以包括耦合到第二本地电源信号的第二多个数据存储单元。 第一开关可以被配置为根据第一选择信号的值将第一本地电源信号选择性地耦合到第一电源信号或第二电源信号，并且第二开关可被配置为选择性地将第二本地电源信号 根据第二选择信号的值将电源信号提供给第一电源信号或第二电源信号。

公开(公告)号：US20140177354A1

公开(公告)日：2014-06-26

申请号：US13725784

申请日：2012-12-21

Applicant: APPLE INC.

Inventor： Hitesh K. Gupta ,  Greg M. Hess ,  Naveen Javarappa

IPC: G11C7/00 ,  H03K19/00

CPC classification number: G11C7/00 ,  G11C29/1201 ,  G11C29/32 ,  G11C29/48 ,  H03K3/356121 ,  H03K3/356173 ,  H03K19/00

Abstract: A zero keeper circuit includes a dynamic input PFET connected to a source, an output, and a dynamic input. The circuit also includes a clock input NFET connected to the output, a pull-down node, and a clock input. The circuit also includes a dynamic input NFET connected to the pull-down node, a reference voltage, and the dynamic input. The circuit also includes a feedback PFET and a clock input PFET connected in series between the source and the output. The feedback PFET receives a feedback signal and the clock input PFET receives the clock input. The circuit also includes a feedback NFET connected to the output and the node. The feedback NFET is configured to couple the output to the node based on the feedback signal. The circuit also includes a NOR gate configured to provide the feedback signal based on the output and a bypass input.

Abstract translation: 零保持器电路包括连接到源，输出和动态输入的动态输入PFET。 电路还包括连接到输出的时钟输入NFET，下拉节点和时钟输入。 电路还包括连接到下拉节点的动态输入NFET，参考电压和动态输入。 电路还包括反馈PFET和在源极和输出端之间串联连接的时钟输入PFET。 反馈PFET接收反馈信号，时钟输入PFET接收时钟输入。 电路还包括连接到输出端和节点的反馈NFET。 反馈NFET被配置为基于反馈信号将输出耦合到节点。 电路还包括被配置为基于输出和旁路输入提供反馈信号的或非门。

公开(公告)号：US08860464B2

公开(公告)日：2014-10-14

申请号：US13725784

申请日：2012-12-21

Applicant: Apple Inc.

Inventor： Hitesh K Gupta ,  Greg M Hess ,  Naveen Javarappa

IPC: H03K3/037 ,  H03K19/00 ,  G11C7/00

CPC classification number: G11C7/00 ,  G11C29/1201 ,  G11C29/32 ,  G11C29/48 ,  H03K3/356121 ,  H03K3/356173 ,  H03K19/00

Abstract: A zero keeper circuit includes a dynamic input PFET connected to a source, an output, and a dynamic input. The circuit also includes a clock input NFET connected to the output, a pull-down node, and a clock input. The circuit also includes a dynamic input NFET connected to the pull-down node, a reference voltage, and the dynamic input. The circuit also includes a feedback PFET and a clock input PFET connected in series between the source and the output. The feedback PFET receives a feedback signal and the clock input PFET receives the clock input. The circuit also includes a feedback NFET connected to the output and the node. The feedback NFET is configured to couple the output to the node based on the feedback signal. The circuit also includes a NOR gate configured to provide the feedback signal based on the output and a bypass input.

Abstract translation: 零保持器电路包括连接到源，输出和动态输入的动态输入PFET。 电路还包括连接到输出的时钟输入NFET，下拉节点和时钟输入。 电路还包括连接到下拉节点的动态输入NFET，参考电压和动态输入。 电路还包括反馈PFET和在源极和输出端之间串联连接的时钟输入PFET。 反馈PFET接收反馈信号，时钟输入PFET接收时钟输入。 电路还包括连接到输出端和节点的反馈NFET。 反馈NFET被配置为基于反馈信号将输出耦合到节点。 电路还包括被配置为基于输出和旁路输入提供反馈信号的或非门。