公开(公告)号：US20240118958A1

公开(公告)日：2024-04-11

申请号：US18529472

申请日：2023-12-05

Applicant: Apple Inc.

Inventor： John H. Kelm ,  Richard H. Larson ,  Charles J. Fleckenstein

IPC: G06F11/07

CPC classification number: G06F11/0757

Abstract: An apparatus includes a memory circuit, and an integrated circuit formed on a single semiconductor substrate and coupled to the memory circuit. The integrated circuit includes a watchdog timer, a plurality of functional circuits coupled together via a communication fabric, and a system management circuit coupled to the watchdog timer and to a subset of the functional circuits via respective dedicated point-to-point interfaces. A given functional circuit may be configured to repeatedly reset the watchdog timer before the watchdog timer expires. The system management circuit may be configured, in response to an expiration of the watchdog timer, to access information in the subset of the functional circuits via the respective point-to-point interfaces. The system management circuit may be further configured to store the accessed information in the memory circuit.

公开(公告)号：US11698671B2

公开(公告)日：2023-07-11

申请号：US17481703

申请日：2021-09-22

Applicant: Apple Inc.

Inventor： Preethi Bhargavi Sama ,  Richard H. Larson ,  Shih-Chieh Wen ,  Srikanth Balasubramanian

IPC: G06F1/32 ,  G06F1/3234

CPC classification number: G06F1/3234

Abstract: Some aspects of this disclosure relate to a peak power manager that includes a first power estimate accumulator circuit configured to receive one or more power estimates associated with one or more subsystems and to generate a first accumulated power estimate. The peak power manage can further include a first-in first-out (FIFO) storage circuit configured to store a plurality of first accumulated power estimates associated with a plurality of clock cycles corresponding to a moving time interval window. The peak power manager can further include a second power estimate accumulator circuit configured to accumulate the plurality of first accumulated power estimates to generate a second accumulated power estimate and a control circuit. The control circuit can be configured to compare the second accumulated power estimate with a threshold power and generate a control signal to control one or more events at the one or more subsystems in response to the second accumulated power estimate satisfying a condition associated with the threshold power.

公开(公告)号：US20180307297A1

公开(公告)日：2018-10-25

申请号：US15496290

申请日：2017-04-25

Applicant: Apple Inc.

Inventor： Bernard Joseph Semeria ,  John H. Mylius ,  Pradeep Kanapathipillai ,  Richard F. Russo ,  Shih-Chieh Wen ,  Richard H. Larson

IPC: G06F1/32 ,  G06F9/38 ,  G06F3/06

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3296 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/067 ,  G06F9/3802

Abstract: Systems, apparatuses, and methods for retaining architected state for relatively frequent switching between sleep and active operating states are described. A processor receives an indication to transition from an active state to a sleep state. The processor stores a copy of a first subset of the architected state information in on-die storage elements capable of retaining storage after power is turned off. The processor supports programmable input/output (PIO) access of particular stored information during the sleep state. When a wakeup event is detected, circuitry within the processor is powered up again. A boot sequence and recovery of architected state from off-chip memory are not performed. Rather than fetch from a memory location pointed to by a reset base address register, the processor instead fetches an instruction from a memory location pointed to by a restored program counter of the retained subset of the architected state information.

公开(公告)号：US20170068575A1

公开(公告)日：2017-03-09

申请号：US14844212

申请日：2015-09-03

Applicant: Apple Inc.

Inventor： James N. Hardage, JR. ,  Daniel U. Becker ,  Christopher M. Tsay ,  Richard F. Russo ,  Shih-Chieh R. Wen ,  Richard H. Larson

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F9/5088 ,  G06F9/30101 ,  G06F9/3828 ,  G06F12/0813 ,  G06F12/084 ,  G06F2212/1028 ,  G06F2212/314 ,  Y02D10/13

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. The processor may support multiple processor states (PStates). Each PState may specify an operating point (e.g. a combination of supply voltage magnitude and clock frequency), and each PState may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core. The context switch may be performed using a special purpose register (SPR) interconnect. Each processor core in a given processor may be coupled to the SPR interconnect to permit access to the external SPRs.

Abstract translation: 在一个实施例中，集成电路可以包括一个或多个处理器。 每个处理器可以包括多个处理器核心，并且每个核心具有不同的设计/实现和性能水平。 处理器可以支持多种处理器状态（PState）。 每个PState可以指定工作点（例如，电源电压幅度和时钟频率的组合），并且每个PState可以映射到处理器核心之一。 在运行期间，其中一个核心是活动的：当前PState映射到的核心。 如果选择新的PState并将其映射到不同的核心，则处理器可以自动地将处理器状态切换到新选择的核心，并且可以在该核心上开始执行。 可以使用专用寄存器（SPR）互连来执行上下文切换。 给定处理器中的每个处理器核心可以耦合到SPR互连以允许访问外部SPR。

公开(公告)号：US09928115B2

公开(公告)日：2018-03-27

申请号：US14844212

申请日：2015-09-03

Applicant: Apple Inc.

Inventor： James N. Hardage, Jr. ,  Daniel U. Becker ,  Christopher M. Tsay ,  Richard F. Russo ,  Shih-Chieh R. Wen ,  Richard H. Larson

IPC: G06F9/50 ,  G06F12/084 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0813

CPC classification number: G06F9/5088 ,  G06F9/30101 ,  G06F9/3828 ,  G06F12/0813 ,  G06F12/084 ,  G06F2212/1028 ,  G06F2212/314 ,  Y02D10/13

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. The processor may support multiple processor states (PStates). Each PState may specify an operating point (e.g. a combination of supply voltage magnitude and clock frequency), and each PState may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core. The context switch may be performed using a special purpose register (SPR) interconnect. Each processor core in a given processor may be coupled to the SPR interconnect to permit access to the external SPRs.

公开(公告)号：US11853148B2

公开(公告)日：2023-12-26

申请号：US17656153

申请日：2022-03-23

Applicant: Apple Inc.

Inventor： John H. Kelm ,  Richard H. Larson ,  Charles J. Fleckenstein

IPC: G06F11/07

CPC classification number: G06F11/0757

Abstract: An apparatus includes a memory circuit, and an integrated circuit formed on a single semiconductor substrate and coupled to the memory circuit. The integrated circuit includes a watchdog timer, a plurality of functional circuits coupled together via a communication fabric, and a system management circuit coupled to the watchdog timer and to a subset of the functional circuits via respective dedicated point-to-point interfaces. A given functional circuit may be configured to repeatedly reset the watchdog timer before the watchdog timer expires. The system management circuit may be configured, in response to an expiration of the watchdog timer, to access information in the subset of the functional circuits via the respective point-to-point interfaces. The system management circuit may be further configured to store the accessed information in the memory circuit.

公开(公告)号：US20230089576A1

公开(公告)日：2023-03-23

申请号：US17656153

申请日：2022-03-23

Applicant: Apple Inc.

Inventor： John H. Kelm ,  Richard H. Larson ,  Charles J. Fleckenstein

IPC: G06F11/07

Abstract: An apparatus includes a memory circuit, and an integrated circuit formed on a single semiconductor substrate and coupled to the memory circuit. The integrated circuit includes a watchdog timer, a plurality of functional circuits coupled together via a communication fabric, and a system management circuit coupled to the watchdog timer and to a subset of the functional circuits via respective dedicated point-to-point interfaces. A given functional circuit may be configured to repeatedly reset the watchdog timer before the watchdog timer expires. The system management circuit may be configured, in response to an expiration of the watchdog timer, to access information in the subset of the functional circuits via the respective point-to-point interfaces. The system management circuit may be further configured to store the accessed information in the memory circuit.

公开(公告)号：US10990159B2

公开(公告)日：2021-04-27

申请号：US15496290

申请日：2017-04-25

Applicant: Apple Inc.

Inventor： Bernard Joseph Semeria ,  John H. Mylius ,  Pradeep Kanapathipillai ,  Richard F. Russo ,  Shih-Chieh Wen ,  Richard H. Larson

IPC: G06F9/38 ,  G06F3/06 ,  G06F1/3287 ,  G06F1/3228 ,  G06F1/3206 ,  G06F1/3296

Abstract: Systems, apparatuses, and methods for retaining architected state for relatively frequent switching between sleep and active operating states are described. A processor receives an indication to transition from an active state to a sleep state. The processor stores a copy of a first subset of the architected state information in on-die storage elements capable of retaining storage after power is turned off. The processor supports programmable input/output (PIO) access of particular stored information during the sleep state. When a wakeup event is detected, circuitry within the processor is powered up again. A boot sequence and recovery of architected state from off-chip memory are not performed. Rather than fetch from a memory location pointed to by a reset base address register, the processor instead fetches an instruction from a memory location pointed to by a restored program counter of the retained subset of the architected state information.