公开(公告)号：US10740527B2

公开(公告)日：2020-08-11

申请号：US15697239

申请日：2017-09-06

Applicant: Apple Inc.

Inventor： Farzan Farbiz ,  Thomas Hoffmann ,  Xin Yi Zhang

IPC: G06F30/30 ,  G06F30/392 ,  H01L27/118 ,  H01L27/092 ,  H01L29/78 ,  G06F30/33 ,  G06F30/39 ,  G06F30/394 ,  H01L27/02

Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.

公开(公告)号：US12087689B2

公开(公告)日：2024-09-10

申请号：US18488561

申请日：2023-10-17

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Jung-Cheng Yeh ,  Kunzhong Hu ,  Raymundo Camenforte ,  Thomas Hoffmann

IPC: H01L21/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/538 ,  H01L23/58 ,  H01L25/065 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L23/481 ,  H01L23/5386 ,  H01L23/585 ,  H01L25/0652 ,  H01L25/0655 ,  H01L21/78 ,  H01L22/20 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/30 ,  H01L24/32 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/30181 ,  H01L2224/32145 ,  H01L2224/32225

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

公开(公告)号：US20230085890A1

公开(公告)日：2023-03-23

申请号：US17483535

申请日：2021-09-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Jung-Cheng Yeh ,  Kunzhong Hu ,  Raymundo Camenforte ,  Thomas Hoffmann

IPC: H01L23/528 ,  H01L23/58 ,  H01L23/538 ,  H01L23/48 ,  H01L25/065

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

公开(公告)号：US20200328205A1

公开(公告)日：2020-10-15

申请号：US16913770

申请日：2020-06-26

Applicant: Apple Inc.

Inventor： Emre Alptekin ,  Thomas Hoffmann

IPC: H01L27/088 ,  H01L27/02 ,  G06F30/398

Abstract: In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.

公开(公告)号：US20250029921A1

公开(公告)日：2025-01-23

申请号：US18792451

申请日：2024-08-01

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Jung-Cheng Yeh ,  Kunzhong Hu ,  Raymundo Camenforte ,  Thomas Hoffmann

IPC: H01L23/528 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H01L23/58 ,  H01L25/065

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

公开(公告)号：US11862557B2

公开(公告)日：2024-01-02

申请号：US17483535

申请日：2021-09-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Jung-Cheng Yeh ,  Kunzhong Hu ,  Raymundo Camenforte ,  Thomas Hoffmann

IPC: H01L21/00 ,  H01L23/528 ,  H01L23/538 ,  H01L23/48 ,  H01L25/065 ,  H01L23/58 ,  H01L21/66 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L23/528 ,  H01L23/481 ,  H01L23/5386 ,  H01L23/585 ,  H01L25/0652 ,  H01L25/0655 ,  H01L21/78 ,  H01L22/20 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/30 ,  H01L24/32 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/30181 ,  H01L2224/32145 ,  H01L2224/32225

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

公开(公告)号：US20230409797A1

公开(公告)日：2023-12-21

申请号：US18337781

申请日：2023-06-20

Applicant: Apple Inc.

Inventor： Farzan Farbiz ,  Thomas Hoffmann ,  Xin Yi Zhang

IPC: G06F30/392 ,  H01L27/118 ,  H01L27/092 ,  H01L29/78 ,  G06F30/33 ,  G06F30/39 ,  G06F30/394

CPC classification number: G06F30/392 ,  H01L27/11807 ,  H01L27/0921 ,  H01L29/785 ,  G06F30/33 ,  G06F30/39 ,  G06F30/394 ,  H01L27/0251

Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.

公开(公告)号：US11720734B2

公开(公告)日：2023-08-08

申请号：US16920524

申请日：2020-07-03

Applicant: Apple Inc.

Inventor： Farzan Farbiz ,  Thomas Hoffmann ,  Xin Yi Zhang

IPC: G06F30/392 ,  H01L27/118 ,  H01L27/092 ,  H01L29/78 ,  G06F30/33 ,  G06F30/39 ,  G06F30/394 ,  H01L27/02

CPC classification number: G06F30/392 ,  G06F30/33 ,  G06F30/39 ,  G06F30/394 ,  H01L27/0921 ,  H01L27/11807 ,  H01L29/785 ,  H01L27/0251 ,  H01L2027/1189

Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.

公开(公告)号：US20200118999A1

公开(公告)日：2020-04-16

申请号：US16156461

申请日：2018-10-10

Applicant: Apple Inc.

Inventor： Emre Alptekin ,  Thomas Hoffmann

IPC: H01L27/088 ,  H01L27/02 ,  G06F17/50

Abstract: In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.

公开(公告)号：US20190073440A1

公开(公告)日：2019-03-07

申请号：US15697239

申请日：2017-09-06

Applicant: Apple Inc.

Inventor： Farzan Farbiz ,  Thomas Hoffmann ,  Xin Yi Zhang

IPC: G06F17/50

Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.