公开(公告)号：US11942141B2

公开(公告)日：2024-03-26

申请号：US17962828

申请日：2022-10-10

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Cyrille Nicolas Dray ,  El Mehdi Boujamaa

IPC: G11C7/10 ,  G11C11/16 ,  G11C11/408 ,  G11C11/4093

CPC classification number: G11C11/4082 ,  G11C7/106 ,  G11C7/1087 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1697 ,  G11C11/4093

Abstract: Various implementations described herein are related to a device having memory circuitry activated by a power-gated supply. The device may include level shifting circuitry that receives a switch control signal in a first voltage domain, shifts the switch control signal in the first voltage domain to a second voltage domain, and provides the switch control signal in the second voltage domain. The device may include power-gating circuitry activated by the switch control signal in the second voltage domain, and the power-gating circuitry may provide the power-gated supply to the memory circuitry to trigger activation of the memory circuitry with the power-gated supply when activated by the switch control signal in the second voltage domain.

公开(公告)号：US11386937B2

公开(公告)日：2022-07-12

申请号：US16600483

申请日：2019-10-12

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Nicolaas Klarinus Johannes Van Winkelhoff ,  Bo Zheng ,  El Mehdi Boujamaa ,  Fakhruddin Ali Bohra

IPC: G11C7/10 ,  G11C11/419 ,  G11C11/418 ,  G11C11/16

Abstract: Various implementations described herein refer to a method for providing single port memory with a bitcell array arranged in columns and rows. The method may include coupling a wordline to the single port memory including coupling the wordline to the columns of the bitcell array. The method may include performing multiple memory access operations concurrently in the single port memory including performing a read operation in one column of the bitcell array using the wordline while performing a write operation in another column of the bitcell array using the wordline, or performing a write operation in one column of the bitcell array using the wordline while performing a read operation in another column of the bitcell array using the same wordline.

公开(公告)号：US20210098032A1

公开(公告)日：2021-04-01

申请号：US16584898

申请日：2019-09-26

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Bo Zheng ,  El Mehdi Boujamaa ,  Fakhruddin Ali Bohra

IPC: G11C7/10 ,  G11C11/419 ,  G11C11/16 ,  G11C11/418

Abstract: Various implementations described herein refer to a method for providing single port memory with multiple different banks having a first bank and a second bank that is different than the first bank. The method may include coupling multiple wordlines to the single port memory including coupling a first wordline to the first bank and coupling a second wordline to the second bank. The method may include performing multiple memory access operations concurrently in the single port memory.

公开(公告)号：US20190325948A1

公开(公告)日：2019-10-24

申请号：US15960475

申请日：2018-04-23

Applicant: Arm Limited

Inventor： Vivek Nautiyal ,  Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC: G11C11/419

Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.

公开(公告)号：US11742001B2

公开(公告)日：2023-08-29

申请号：US16860764

申请日：2020-04-28

Applicant: Arm Limited

Inventor： Fakhruddin Ali Bohra ,  Lalit Gupta ,  Shri Sagar Dwivedi

IPC: G11C7/10

CPC classification number: G11C7/1012 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1078

Abstract: Various implementations described herein are related to a device having memory circuitry having an array of memory cells. The device may include output circuitry coupled to the memory circuitry, and the output circuitry may have a first set of multiplexers that receives column data from the array of memory cells and provides first multiplexed output data. The device may include output interface circuitry coupled to the output circuitry, and the output interface circuitry may have a second set of multiplexers that receives the first multiplexed output data from the output circuitry and selectively provides second multiplexed output data based on a configurable mode of multiplexed operation.

公开(公告)号：US20220060186A1

公开(公告)日：2022-02-24

申请号：US17000147

申请日：2020-08-21

Applicant: Arm Limited

Inventor： Lalit Gupta ,  El Mehdi Boujamaa ,  Tirdad Anthony Takeshian

IPC: H03K19/0185 ,  H03K3/037

Abstract: Various implementations described herein are related to a device having level shifter circuitry configured to receive isolation control signals in a first voltage domain and provide an output signal in a second voltage domain that is different than the first voltage domain. The device may include isolation logic circuitry configured to receive a data input signal in the first voltage domain and then provide the isolation control signals to the level shifter circuitry in the first voltage domain based on the data input signal. The isolation logic circuitry may include control passgates that enable the data input signal to propagate to the level shifter circuitry via the isolation control signals.

公开(公告)号：US20210110851A1

公开(公告)日：2021-04-15

申请号：US16709687

申请日：2019-12-10

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Nicolaas Klarinus Johannes Van Winkelhoff ,  El Mehdi Boujamaa ,  Bo Zheng ,  Fakhruddin Ali Bohra ,  Cyrille Nicolas Dray ,  Ashish Bhardwaj ,  Durgesh Kumar Dubey

IPC: G11C7/10 ,  G11C8/08

Abstract: Various implementations described herein are directed to an implementation of a higher order multiplexer using lower order multiplexers. In an embodiment, the implementation requires a slight modification to the existing circuitry design of the lower multiplexers. A plurality of multiplexers may be coupled with each other such that a common input port and output port is formed. Using an enable signal, only one of the coupled multiplexers may be enabled at a time while the remaining multiplexers are switched off. Therefore, upon receiving a select signal indicating an address of a memory cell, the lower multiplexers coupled together function as a higher order multiplexer in selecting the appropriate column corresponding to the memory cell.

公开(公告)号：US20210065839A1

公开(公告)日：2021-03-04

申请号：US16555964

申请日：2019-08-29

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Gaurav Rattan Singla

IPC: G11C29/00 ,  G11C11/4091 ,  G11C11/16 ,  G11C8/18

Abstract: Various implementations described herein are directed to a device having memory with an array of bitcells arranged in columns and rows, wherein a first number of columns represents a first number of output bits, and a second number of columns represents a second number of output bits. The device may include dummy wordline (DWL) circuitry having multiple DWL paths including a first DWL path disposed along the first number of columns and a second DWL path disposed along the second number of columns. The first DWL path has a shorter length than the second DWL path so as to allow for faster operation of the bitcells in the memory associated with the first number of output bits.

公开(公告)号：US20190244656A1

公开(公告)日：2019-08-08

申请号：US15891212

申请日：2018-02-07

Applicant: Arm Limited

Inventor： Yicong Li ,  Andy Wangkun Chen ,  Sharryl Renee Dettmer ,  Lalit Gupta ,  Jitendra Dasani ,  Yeon Jun Park ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra

IPC: G11C11/4097 ,  G11C7/18 ,  G11C11/419 ,  H01L27/11

Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry. The memory circuitry may include a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair. The integrated circuit may include first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry. The integrated circuit may include second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs. The first bitline pair and the second bitline pair may be on a lower metal layer, and the jumper bitline pairs may be on a higher metal layer.

公开(公告)号：US20190066770A1

公开(公告)日：2019-02-28

申请号：US15684255

申请日：2017-08-23

Applicant: ARM Limited

Inventor： Rajiv Kumar Sisodia ,  Navin Agarwal ,  Shri Sagar Dwivedi ,  Jitendra Dasani ,  Fakhruddin Ali Bohra ,  Lalit Gupta ,  Daksheshkumar Maganbhai Malaviya

IPC: G11C11/419

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include read circuitry coupled to bitlines, and the read circuitry may be activated based on a read select signal to perform a read operation on the bitlines. The integrated circuit may include write circuitry coupled to the bitlines, and the write circuitry may be activated based on a write select signal to perform a write operation on the bitlines. The integrated circuit may include bitline discharge control circuitry coupled to the bitlines and the write circuitry, and the bitline discharge control circuitry may control the bitline discharge of the bitlines during the read operation so as to restrict a false read on the bitlines by providing a discharge boundary for the bitlines during the read operation.