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公开(公告)号：US20200073660A1
公开(公告)日：2020-03-05
申请号：US16118528
申请日：2018-08-31
Applicant: Arm Limited
Inventor： Xiaoyang SHEN , Cedric Denis Robert AIRAUD , Luca NASSI , Damien Robin MARTIN
Abstract: Apparatus comprises counter and bit-shift circuitry to provide a succession of processing stages each comprising a count operation stage and a corresponding bit-shift stage, each processing stage operating with respect to a set of contiguous n-bit groups of bit positions, where n is 1 for a first processing stage and n doubles from one processing stage in the succession of processing stages to a next processing stage in the succession of processing stages; each count operation stage being configured to generate, for a first set of alternate instances of the n-bit groups of bit positions, count values indicating a respective number of bits of a predetermined bit value in a mask data word; and each bit-shift stage being configured to generate a bit-shifted data word by bit-shifting bits of a data word to be processed, for a second set of alternate instances of the n-bit groups of bit positions complementary to the first set, by respective numbers of bit positions dependent upon the count values generated by the respective count operation stage, in which the bit-shifted data word for one bit-shift stage in the succession of processing stages is used as the data word to be processed by the next bit-shift stage in the succession of processing stages.
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公开(公告)号：US20240126458A1
公开(公告)日：2024-04-18
申请号：US17966071
申请日：2022-10-14
Applicant: Arm Limited
Inventor： Stefano GHIGGINI , Natalya Bondarenko , Luca NASSI , Geoffray Matthieu LACOURBA , Huzefa Moiz SANJELIWALA , Miles Robert DOOLEY , . ABHISHEK RAJA
IPC: G06F3/06
CPC classification number: G06F3/0634 , G06F3/0604 , G06F3/0659 , G06F3/0673
Abstract: An apparatus is provided for controlling the operating mode of control circuitry, such that the control circuitry may change between two operating modes. In an allocation mode, data that is loaded in response to an instruction is allocated into storage circuitry from an intermediate buffer, and the data is read from the storage circuitry. In a non-allocation mode, the data is not allocated to the storage circuitry, and is read directly from intermediate buffer. The control of the operating mode may be performed by mode control circuitry, and the mode may be changed in dependence on the type of instruction that calls the data, and whether the data may be used again in the near future, or whether it is expected to be used only once.
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公开(公告)号：US20190377706A1
公开(公告)日：2019-12-12
申请号：US16005790
申请日：2018-06-12
Applicant: Arm Limited
Inventor： Cedric Denis Robert AIRAUD , Luca NASSI , Damien Robin MARTIN , Xiaoyang SHEN
Abstract: Apparatuses and methods of data processing are disclosed. An apparatus comprises two data processing clusters each having multiple data processing lanes to perform single instruction multiple data (SIMD) processing. Decoded instructions are issued to at least one of the two data processing clusters. A decoded SIMD instruction specifying a vector length which is more than the width of the data processing lanes of the first data processing cluster has a first part issued to the first data processing cluster for execution. An issuance target for a second remaining part of the decoded SIMD instruction is selected in dependence on a dynamic performance condition. When the dynamic performance condition has a first state the issuance target is the first data processing cluster and when the dynamic performance condition has a second state the issuance target is the second data processing cluster. When the issuance target is the first data processing cluster, to schedule the first and second parts of the decoded SIMD instruction in series.
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公开(公告)号：US20240241723A1
公开(公告)日：2024-07-18
申请号：US18096141
申请日：2023-01-12
Applicant: Arm Limited
Inventor： Luca NASSI , Geoffray Matthieu LACOURBA , Cédric Denis Robert AIRAUD , Albin Pierrick TONNERRE
CPC classification number: G06F9/30098 , G06F9/30094 , G06F9/384
Abstract: A data processing apparatus is provided. Instruction send circuitry sends an instruction to an external processor to be executed by the external processor. Allocation circuitry allocates a specified one of several registers for a result of the instruction having been executed on the external processor and data receive circuitry receives the result of the instruction having been executed on the external processor and stores the result in the specified one of the several registers. In response to a condition being met: the specified one of the several registers is dereserved prior to the result being received by the data receive circuitry, and the result is discarded by the data receive circuitry when the result is received by the data receive circuitry.
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公开(公告)号：US20230385199A1
公开(公告)日：2023-11-30
申请号：US17824199
申请日：2022-05-25
Applicant: Arm Limited
Inventor： Damien Matthieu Valentin CATHRINE , Ugo CASTORINA , Luca NASSI
IPC: G06F12/0862
CPC classification number: G06F12/0862 , G06F2212/602
Abstract: An apparatus comprises prefetch circuitry, and a cache having a plurality of entries to store data for access by processing circuitry and blocks of metadata for reference by the prefetch circuitry. The prefetch circuitry can detect one or more access sequences in dependence on training inputs derived from demand accesses processed by the cache in response to memory access operations performed by the processing circuitry. On detecting a given access sequence, this causes an associated given block of metadata providing information indicative of the given access sequence to be stored in a selected entry of the cache. Eviction control circuitry, responsive to a victimisation event, performs an operation to select a victim entry in the cache, the victim entry being selected from one or more candidate victim entries. Each entry has an associated age indication value used to determine whether that entry is allowed to be a candidate victim entry, and the eviction control circuitry is arranged to perform a dynamic ageing operation to determine an ageing control value used to control updating of the associated age indication value for any entry storing a block of metadata. The dynamic ageing operation is arranged to determine the ageing control value in dependence on at least a training rate indication for the prefetch circuitry, where the training rate indication is indicative of a number of training inputs per memory access operation performed by the processing circuitry.
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Patent Agency Ranking
公开(公告)号：US20190303161A1
公开(公告)日：2019-10-03
申请号：US15939827
申请日：2018-03-29
Applicant: Arm Limited
Inventor： Luca NASSI , Houdhaifa BOUZGUARROU , Guillaume BOLBENES
Abstract: An apparatus and method are provided for controlling branch prediction. The apparatus has processing circuitry for executing instructions, and branch prediction circuitry that comprises a plurality of branch prediction mechanisms used to predict target addresses for branch instructions to be executed by the processing circuitry. The branch instructions comprise a plurality of branch types, where one branch type is a return instruction. The branch prediction mechanisms include a return prediction mechanism used by default to predict a target address when a return instruction is detected by the branch prediction circuitry. However, the branch prediction circuitry is responsive to a trigger condition indicative of misprediction of the target address when using the return prediction mechanism to predict the target address for a given return instruction, to switch to using an alternative branch prediction mechanism for predicting the target address for the given return instruction. This has been found to improve performance in certain situations.
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公开(公告)号：US20250004767A1
公开(公告)日：2025-01-02
申请号：US18345164
申请日：2023-06-30
Applicant: Arm Limited
IPC: G06F9/30
Abstract: Mode change detection circuitry detects a mode change when processing circuitry switches between first and second modes of processing in which a first set of architectural registers are designated as having different register lengths. Register mapping circuitry maps architectural registers to corresponding physical registers. For an operation specifying a given architectural register of the first set of architectural registers: in response to a determination that the operation is to be processed in the first mode of processing, the register mapping circuitry maps the given architectural register to a physical register of a first physical register file, and in response to a determination that the operation is to be processed in the second mode of processing, the register mapping circuitry maps the given architectural register to a physical register of a second physical register file separate from the first physical register file and having physical registers of different register length to physical registers of the first physical register file.
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8.发明公开公开(公告)号：US20240256281A1
公开(公告)日：2024-08-01
申请号：US18101726
申请日：2023-01-26
Applicant: Arm Limited
Inventor： Quentin Éric NOUVEL , Luca NASSI , Adrien PESLE
IPC: G06F9/38
CPC classification number: G06F9/384
Abstract: A data processing apparatus comprises: execution circuitry to execute instructions in order to perform data processing operations specified by those instructions; a plurality of registers to store data values for access by the execution circuitry when performing the data processing operations, each register having an associated physical register identifier; register rename circuitry to select physical register identifiers to associate with architectural register identifiers specified by the instructions; and rename storage having a plurality of entries, each entry being associated with one of the architectural register identifiers and used by the register rename circuitry to indicate a physical register identifier selected for association with that one of the architectural register identifiers; the register rename circuitry comprising an execute unit, and being responsive to detection of an early execute condition for a given instruction, the early execute condition requiring at least detection that each source value required to execute the given instruction is available to the register rename circuitry without accessing the plurality of registers, to cause the execute unit to perform the data processing operation specified by the given instruction in order to generate a result value, and to cause the generated result value to be stored in an entry of the rename storage associated with a destination architectural register identifier specified by the given instruction.
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公开(公告)号：US20220374240A1
公开(公告)日：2022-11-24
申请号：US17326864
申请日：2021-05-21
Applicant: Arm Limited
Inventor： Damian MAIORANO , Luca NASSI , Cédric Denis Robert AIRAUD , Christophe Laurent CARBONNE , Jocelyn François Orion JAUBERT , Pasquale RANONE
Abstract: Data processing circuitry comprises out-of-order instruction execution circuitry; register mapping circuitry to map zero or more architectural processor registers relating to execution of that program instruction to respective ones of a set of physical processor registers; commit circuitry to commit, in a program code order, the results of executed program instructions, the commit circuitry being configured to access a data store which stores register tag data to indicate which physical registers mapped by the register mapping circuitry relate to a given program instruction; fault detection circuitry to detect a memory access fault in respect of a vector memory access operation and to generate fault indication data indicative of an element earliest in the element order for which a memory access fault was detected; a fault indication register to store the fault indication data, in which the register mapping circuitry is configured to generate a register mapping for a program instruction for any architectural processor registers relating to execution of that program instruction other than the fault indication register; and control circuitry to encode the fault indication data, applicable to a program instruction not yet committed by the commit circuitry, to register tag data associated with that program instruction.
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公开(公告)号：US20200065109A1
公开(公告)日：2020-02-27
申请号：US16524667
申请日：2019-07-29
Applicant: Arm Limited
Inventor： Xiaoyang SHEN , Damien Robin MARTIN , Cédric Denis Robert AIRAUD , Luca NASSI , François DONATI
Abstract: An apparatus has a processing pipeline, and first and second register files. A temporary-register-using instruction is supported which controls the pipeline to perform an operation using a temporary variable derived from an operand stored in the first register file. In response to the instruction, when a predetermined condition is not satisfied, the pipeline processes at least one register move micro-operation to transfer data from the at least one source register of the first register file to at least one newly allocated temporary register of the second register file. When the condition is satisfied, the operation can be performed using a temporary variable already stored in the temporary register of the second register file used by an earlier temporary-register-using instruction specifying the same source register for determining the temporary variable, in the absence of an intervening instruction for rewriting the source register.
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