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    ADDRESS TRANSLATION IN A DATA PROCESSING APPARATUS
    1.
    发明申请
    ADDRESS TRANSLATION IN A DATA PROCESSING APPARATUS 有权
    数据处理设备中的地址翻译

    公开(公告)号：US20150178220A1

    公开(公告)日：2015-06-25

    申请号：US14579483

    申请日：2014-12-22

    Applicant: ARM Limited

    Inventor： Roko GRUBISIC ,  Andrew BURDASS ,  Daren CROXFORD ,  Isidoros SIDERIS

    IPC: G06F12/10

    CPC classification number: G06F12/1027 ,  G06F2212/304 ,  Y02D10/13

    Abstract: Address translation circuitry and a method of operating such a translation circuitry are provided. The address translation circuitry is configured to receive a first address used in a first addressing system and to translate it into a second address used in a second addressing system. Translation pipeline circuitry has plural pipeline stages configured to translate the first address into the second address over the course of the plural pipeline stages. Address comparison circuitry is configured to identify an address match condition when a received first address at least partially matches a previously received first address. Insertion circuitry is configured to determine a stage of progress of the previously received first address in the plural pipeline stages and to cause content of the stage of progress of the previously received first address to be unchanged at a next pipeline cycle when the address comparison circuitry identifies the address match condition.

    Abstract translation: 提供地址转换电路和操作这种翻译电路的方法。 地址转换电路被配置为接收在第一寻址系统中使用的第一地址并将其转换成在第二寻址系统中使用的第二地址。 翻译流水线电路具有多个流水线级，配置成在多个流水线阶段的过程中将第一地址转换为第二地址。 地址比较电路被配置为当接收到的第一地址至少部分匹配先前接收到的第一地址时，识别地址匹配条件。 插入电路被配置为确定多个流水线级中先前接收到的第一地址的进展阶段，并且当地址比较电路识别时，使下一个流水线周期使先前接收的第一地址的进展阶段的内容不变 地址匹配条件。

    SPECULATIVE BUFFER
    2.
    发明申请
    SPECULATIVE BUFFER 有权

    公开(公告)号：US20210157597A1

    公开(公告)日：2021-05-27

    申请号：US16695735

    申请日：2019-11-26

    Applicant: Arm Limited

    Inventor： Roko GRUBISIC

    IPC: G06F9/38 ,  G06F12/0875

    Abstract: An apparatus comprises processing circuitry to execute instructions from one or more of a plurality of execution contexts each associated with a respective execution context identifier; a cache; and a speculative buffer. Control circuitry controls allocation of data to the cache and the speculative buffer. A speculative entry, for which allocation is caused by a speculative memory access associated with a given execution context, is allocated to the speculative buffer instead of to the cache while the speculatively executed memory access instruction remains speculative. The speculative entry specifies, as a tagged execution context identifier, the execution context identifier associated with the given execution context. Presence of the speculative entry in the speculative buffer is prevented from being observable to execution contexts other than the execution context identified by the tagged execution context identifier.

    DATA PROCESSING APPARATUS HAVING A CACHE
    3.
    发明申请
    DATA PROCESSING APPARATUS HAVING A CACHE 审中-公开
    具有高速缓存的数据处理设备

    公开(公告)号：US20160321182A1

    公开(公告)日：2016-11-03

    申请号：US15099119

    申请日：2016-04-14

    Applicant: ARM Limited

    Inventor： Roko GRUBISIC ,  Hakan PERSSON ,  Neil Andrew JAMESON

    IPC: G06F12/08 ,  G06F12/12 ,  G06F12/10 ,  G06F9/46

    CPC classification number: G06F12/0833 ,  G06F12/1027 ,  G06F2212/652 ,  G06F2212/681 ,  G06F2212/683

    Abstract: An apparatus has a cache configured to store entries which correspond to blocks of addresses having one of a plurality of sizes as selected by a control device. When the control device has not yet indicated which size to use, cache access circuitry assumes a default size which is greater than at least one of the plurality of sizes.

    Abstract translation: 一种装置具有缓存，其被配置为存储对应于由控制装置选择的具有多个尺寸中的一个的地址块的条目。 当控制设备尚未指示要使用哪个大小时，高速缓存访​​问电路采用大于多个尺寸中的至少一个的默认大小。

    CIRCUITRY AND METHODS
    4.
    发明申请
    CIRCUITRY AND METHODS 有权

    公开(公告)号：US20210124585A1

    公开(公告)日：2021-04-29

    申请号：US16662396

    申请日：2019-10-24

    Applicant: Arm Limited

    Inventor： Roko GRUBISIC ,  Giacomo GABRIELLI ,  Matthew James HORSNELL ,  Syed Ali Mustafa ZAIDI

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Circuitry comprises decode circuitry to decode program instructions including producer instructions and consumer instructions, a consumer instruction requiring, as an input operand, a result generated by execution of a producer instruction; and execution circuitry to execute the program instructions; in which: the decode circuitry is configured to control operation of the execution circuitry in response to hint data associated with a given producer instruction and indicating, for the given producer instruction, a number of consumer instructions which require, as an input operand, a result generated by the given producer instruction.

    DATA STORAGE
    5.
    发明申请
    DATA STORAGE 审中-公开

    公开(公告)号：US20170090791A1

    公开(公告)日：2017-03-30

    申请号：US15256942

    申请日：2016-09-06

    Applicant: ARM LIMITED

    Inventor： Roko GRUBISIC ,  Häkan Lars-Göran PERSSON ,  Georgia KOUVELI

    IPC: G06F3/06 ,  G06F12/1018

    CPC classification number: G06F3/0619 ,  G06F3/0644 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0804 ,  G06F12/0864 ,  G06F12/0866 ,  G06F12/0895 ,  G06F12/1018 ,  Y02D10/13

    Abstract: A data storage device comprises an array of data storage elements arranged as multiple partitions each comprising two or more data storage elements, each data storage element being associated with a respective identifier which identifies a data item currently stored by that data storage element; a predictor configured to compare, for each partition, information derived from the identifiers associated with the data storage elements of that partition with information derived from an identifier associated with the required data item, to identify a subset of partitions that do not store the required data item; and a comparator configured to compare identifiers associated with data storage elements of one or more partitions with the identifier associated with the required data item, wherein any partitions in the subset of partitions are excluded from the test group of partitions.

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