公开(公告)号：US11914543B2

公开(公告)日：2024-02-27

申请号：US17543170

申请日：2021-12-06

Applicant: Arm Limited

Inventor： Tessil Thomas

IPC: G06F13/24 ,  G06F13/42 ,  G06F12/02 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F12/0238 ,  G06F13/1673 ,  G06F13/404 ,  G06F13/4045

Abstract: A data processing apparatus is provided, that includes communication configured for receiving, from an origin Peripheral Component Interconnect Express (PCIe) device, a translated PCIe packet comprising a destination field that comprises a physical address of a destination PCIe device. Permission circuitry transmits a permission check packet, separate to the translated PCIe packet, to a root port to determine whether the origin PCIe device has permission to access the destination PCIe device. Buffer circuitry stores the translated PCIe packet until a response to the permission check packet is received.

公开(公告)号：US11860811B2

公开(公告)日：2024-01-02

申请号：US17702651

申请日：2022-03-23

Applicant: Arm Limited

Inventor： Arthur Brian Laughton ,  Tessil Thomas ,  Jacob Joseph

IPC: G06F13/42 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/1668 ,  G06F13/4059 ,  G06F13/4063

Abstract: The present disclosure provides a system and methods for transferring data across an interconnect. One method includes, at a request node, receiving, from a source high speed serial controller, a write request from a source, dividing the write request into sequences of smaller write requests each having a last identifier, and sending, to a home node, the sequences of smaller write requests; and, at the home node, sending, to a destination high speed serial controller, the sequences of smaller write requests for assembly into intermediate write requests that are transmitted to a destination. Each sequence of smaller write requests is assembled into an intermediate write request based on the last identifier.

公开(公告)号：US11803506B2

公开(公告)日：2023-10-31

申请号：US17512758

申请日：2021-10-28

Applicant: Arm Limited

Inventor： Tessil Thomas ,  Anitha Kona ,  Jacob Joseph ,  Arthur Brian Laughton ,  Nandakishore Sastry

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0026

Abstract: A data processing apparatus is provided that includes communication circuitry to transmit an interconnect message to a root port using a physical address mapped to the root port. Translation circuitry encapsulates, within the interconnect message to the root port, a Peripheral Component Interconnect Express (PCIe) message to a destination, the PCIe message having routing information encoded as a PCIe bus number associated with the destination.

公开(公告)号：US11507514B2

公开(公告)日：2022-11-22

申请号：US16782316

申请日：2020-02-05

Applicant: Arm Limited

Inventor： Tessil Thomas ,  Jan-Peter Larsson

IPC: G06F12/00 ,  G06F12/0891 ,  G06F12/0873 ,  G06F12/0882 ,  G06F12/1027 ,  G06F12/109 ,  G06F12/1081 ,  G06F11/30 ,  G06F7/58 ,  H04L9/06 ,  H04L9/08 ,  G06F11/07 ,  H04L9/32

Abstract: An apparatus is provided, connectable to a memory and one or more peripherals. The apparatus includes translation request circuitry to receive a translation request from one of the peripherals to translate an input address within an input domain to an output address within an output domain. Signing circuitry generates a signature of at least part of the output address using a private key. Translation response circuitry responds to the translation request by transmitting to the one of the peripherals a translation response, including the output address and the signature. Gateway circuitry receives access requests to the memory. Each of the access requests comprises a desired memory address in the output domain and a signature of the desired memory address. The gateway performs validation of the signature of the desired memory address using the private key and in response to the validation of a given access request failing, performs an error action.

公开(公告)号：US20240193260A1

公开(公告)日：2024-06-13

申请号：US18553934

申请日：2022-02-14

Applicant: Arm Limited

Inventor： Tessil Thomas ,  Yuval Elad ,  Thanunathan Rangarajan ,  Carlos Garcia-Tobin

IPC: G06F21/53

CPC classification number: G06F21/53

Abstract: An apparatus and method are provided, the apparatus comprising: interconnect circuitry to couple a device to one or more processing elements, each processing element operating in a trusted execution environment; and secure stashing decision circuitry to receive stashing transactions from the device and to redirect permitted stashing transactions to a given storage structure accessible to at least one of the one or more processing elements. The secure stashing decision circuitry is configured, in response to receiving a given stashing transaction, to determine whether the given stashing transaction comprises a trusted execution environment identifier associated with a given trusted execution environment, and to treat the given stashing transaction as a permitted stashing transaction when redirection requirements, dependent on the trusted execution environment identifier, are met.

公开(公告)号：US11153231B2

公开(公告)日：2021-10-19

申请号：US16516698

申请日：2019-07-19

Applicant: Arm Limited

Inventor： Tessil Thomas ,  Andrew Joseph Rushing

IPC: H04L12/861 ,  H04L12/741 ,  G06F12/0804 ,  G06F3/06

Abstract: An apparatus and method are provided for processing flush requests within a packet network. The apparatus comprises a requester device within the packet network arranged to receive a flush request generated by a remote agent requesting that one or more data items be flushed to a point of persistence. The requester device translates the flush request into a packet-based flush command conforming to a packet protocol of the packet network. A completer device within the packet network that is coupled to a persistence domain incorporating the point of persistence is arranged to detect receipt of the packet-based flush command, and then trigger a flush operation within the persistence domain to flush the one or more data items to the point of persistence. This provides a fast, hardware-based, mechanism for performing a flush operation within a persistence domain without needing to trigger software in the persistence domain to handle the flush to the point of persistence.

公开(公告)号：US10853271B2

公开(公告)日：2020-12-01

申请号：US16053899

申请日：2018-08-03

Applicant: Arm Limited

Inventor： Tessil Thomas ,  Jamshed Jalal ,  Andrea Pellegrini ,  Anitha Kona

IPC: G06F12/14 ,  G06F12/1081 ,  G06F13/42

Abstract: An apparatus includes a first device configured to generate a transaction request targeted to a first address, a switch, coupled to the first device and configured to the route the transaction request, a port coupled to the peripheral switch and the data processing network, and a system memory management unit, coupled to the port. The system memory management unit is configured for receiving an address query for the first address from the peripheral port translating the first address to a second address, accessing attributes of a device associated with the second address and responding to the query. Access validation for the transaction request is confirmed or denied dependent upon the second address and the attributes of the device associated with the second address. The first device may be a peripheral device, the switch may be a peripheral switch and the port may be a peripheral port.

公开(公告)号：US12242399B2

公开(公告)日：2025-03-04

申请号：US17678174

申请日：2022-02-23

Applicant: Arm Limited

Inventor： Jacob Joseph ,  Tessil Thomas ,  Arthur Brian Laughton ,  Anitha Kona ,  Jamshed Jalal

IPC: G06F13/00 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/1045 ,  G06F13/16

Abstract: Peripheral components, data processing systems and methods of operating such peripheral components and data processing systems are disclosed. The systems comprise an interconnect comprising a system cache, a peripheral component coupled to the interconnect, and a memory coupled to the interconnect. The peripheral component has a memory access request queue for queuing memory access requests in a receipt order. Memory access requests are issued to the interconnect in the receipt order. A memory read request is not issued to the interconnect until a completion response for all older memory write requests has been received from the interconnect. The peripheral component is responsive to receipt of a memory read request to issue a memory read prefetch request comprising a physical address to the interconnect and the interconnect is responsive to the memory read prefetch request to cause data associated with the physical address in the memory to be cached in the system cache.

公开(公告)号：US11972142B2

公开(公告)日：2024-04-30

申请号：US17136510

申请日：2020-12-29

Applicant: Arm Limited

Inventor： Tessil Thomas

IPC: G06F3/06 ,  G06F12/0804

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0804 ,  G06F2212/1032

Abstract: Circuitry comprises packet reception circuitry to receive a data communication packet with a storage classification from sending circuitry, the data communication packet including at least payload data and a target address for storage of the payload data; and storage control circuitry to control writing of the payload data of a given data communication packet by one or more storage devices selected from a set of two or more candidate storage devices each addressable by the target address, the storage control circuitry being responsive to the storage classification received with the given data communication packet and to respective persistence properties associated with the set of two or more candidate storage devices.

公开(公告)号：US10359831B2

公开(公告)日：2019-07-23

申请号：US15447866

申请日：2017-03-02

Applicant: ARM Limited

Inventor： Ashley John Crawford ,  Andrew Christopher Rose ,  Tessil Thomas ,  David Guillen Fandos

IPC: G06F1/3225 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296

Abstract: A method of operating a cache and corresponding apparatus are provided. The cache is capable of being only partially powered, and a decision to reduce the proportion of the cache which is currently powered is made based on calculating a memory bandwidth equivalent of expending the current active cache leakage power on memory access. The cache hit bandwidth is compared against this memory bandwidth equivalent and when the cache hit bandwidth is less than the memory bandwidth equivalent, the proportion of the cache which is currently powered is reduced. A analogous decision may also be made and based on calculating a cache hit bandwidth equivalent for an increment increase in cache leakage power, and when the cache miss bandwidth exceeds the cache hit bandwidth equivalent, the proportion of the cache which is currently powered is increased.