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    Phase coherent frequency synthesis
    1.
    发明授权
    Phase coherent frequency synthesis 有权

    公开(公告)号：US11303287B1

    公开(公告)日：2022-04-12

    申请号：US17188518

    申请日：2021-03-01

    Applicant: BAE Systems Information and Electronic Systems Integration Inc.

    Inventor： Steven E. Turner ,  Joseph D. Cali

    IPC: G06F1/02 ,  H03L7/093 ,  H03M3/00

    Abstract: Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.

    MODIFIED DELTA-SIGMA MODULATOR FOR PHASE COHERENT FREQUENCY SYNTHESIS APPLICATIONS
    2.
    发明申请
    MODIFIED DELTA-SIGMA MODULATOR FOR PHASE COHERENT FREQUENCY SYNTHESIS APPLICATIONS 有权
    用于相位频率合成应用的改进型DELTA-SIGMA调制器

    公开(公告)号：US20160173111A1

    公开(公告)日：2016-06-16

    申请号：US14968180

    申请日：2015-12-14

    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

    Inventor： Joseph D. Cali ,  Steven E. Turner

    IPC: H03L7/18 ,  H03M3/00

    CPC classification number: H03L7/1806 ,  H03L7/1976 ,  H03M7/3033

    Abstract: A phase coherent fractional-N phase-locked loop synthesizer for maintaining phase coherence of a synthesized frequency includes a phase coherent delta-sigma modulator (DSM) having a plurality of feed-forward accumulator stages. The DSM is operatively coupled to a reference clock configured to generate a cyclical reference signal. The DSM configured to count a number of cycles of the reference signal, to cause, at each cycle of the reference signal, each of the stages of the DSM to accumulate a sum of a previous stage of the DSM, and to multiply each sum by a fractional divide word to produce a multiplier output, thereby causing the DSM to output a sequence of signals that tracks with the reference clock.

    Abstract translation: 用于维持合成频率的相位相干分数N锁相环合成器包括具有多个前馈累加器级的相位相干Δ-Σ调制器（DSM）。 DSM可操作地耦合到被配置为生成循环参考信号的参考时钟。 DSM被配置为对参考信号的多个周期进行计数，以在每个参考信号周期使DSM的每个级累积DSM的前一级的和，并将每个和乘以 一个分数除法字以产生乘法器输出，从而使得DSM输出与参考时钟一起跟踪的信号序列。

    ROUTING TOPOLOGY FOR DIGITAL SIGNALS WITH RESISTIVE COMBINERS FOR REDUCED JITTER
    3.
    发明申请
    ROUTING TOPOLOGY FOR DIGITAL SIGNALS WITH RESISTIVE COMBINERS FOR REDUCED JITTER 审中-公开

    公开(公告)号：US20190334838A1

    公开(公告)日：2019-10-31

    申请号：US15963594

    申请日：2018-04-26

    Applicant: BAE Systems Information and Electronic Systems Integration Inc.

    Inventor： Mark D. Hickle ,  Joseph D. Cali ,  Lawrence J. Kushner

    IPC: H04L12/931 ,  H04L12/861

    Abstract: A signal routing circuit is disclosed which employs resistive combiners to reduce signal jitter. A signal routing circuit configured according to an embodiment comprises an input stage including a plurality of buffer circuits. Each of the buffer circuits is controlled by a selection signal to enable an input signal at an input port of the buffer circuit to generate an output signal at an output port of the buffer circuit. The signal routing circuit also includes a plurality of resistors to couple the output port of each of the buffer circuits of the input stage to a summing junction. The signal routing circuit further includes an output stage including an additional buffer circuit. The input port of the additional buffer circuit is coupled to the summing junction, and the output port of the additional buffer circuit is configured to provide the routed output signal based on the selection signals.

    Direct Digital Synthesizer With Frequency Correction
    5.
    发明申请
    Direct Digital Synthesizer With Frequency Correction 有权

    公开(公告)号：US20220407524A1

    公开(公告)日：2022-12-22

    申请号：US17351529

    申请日：2021-06-18

    Applicant: BAE Systems Information and Electronic Systems Integration Inc.

    Inventor： Shailendra Srinivas ,  Joseph D. Cali ,  Steven E. Turner

    IPC: H03L7/093

    Abstract: A direct digital synthesizer (DDS) circuit. The circuit includes a first input to receive a first fixed frequency clock signal having a first frequency, a second input to receive a second fixed frequency clock signal having a second frequency lower than the first frequency, and an output to provide an output frequency that is based at least in part on a frequency control word (FCW). The DDS circuit may include a frequency correction circuit having a first input to receive the first clock signal, a second input to receive the second clock signal, and a third input to receive the FCW, and an output to provide a frequency error of the first clock signal, the frequency error determined using the second clock signal and FCW. Alternatively, or in addition to, the DDS circuit may include an all-digital phase lock loop to correct for frequency wander of the first clock signal.

    N-path cascode transistor output switch for a digital to analog converter
    6.
    发明授权
    N-path cascode transistor output switch for a digital to analog converter 有权
    用于数模转换器的N路径共源共栅晶体管输出开关

    公开(公告)号：US09450595B2

    公开(公告)日：2016-09-20

    申请号：US14958051

    申请日：2015-12-03

    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

    Inventor： Joseph D. Cali ,  Lawrence J. Kushner ,  Steven E. Turner

    IPC: H03M1/66 ,  H03M1/06 ,  H01L29/737 ,  H01L29/73 ,  H01L27/06

    CPC classification number: H03M1/0626 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0617 ,  H01L27/088 ,  H03K17/693 ,  H03M1/66 ,  H03M1/742

    Abstract: Techniques are provided for a switched output digital to analog converter employing an N-path cascode output switch. An example system may include a plurality of cascode transistors coupled in parallel to an output stage of a current mode digital to analog converter (DAC) circuit. The system may also include a plurality of control ports, each of the control ports coupled to a gate of one of the cascode transistors. The system may further include a plurality of output ports, each output port coupled to one of the cascode transistors. The cascode transistors are configured to switch the output stage of the DAC to the output port of the transistor in response to a routing control signal applied to the control port of the transistor. The cascode transistors are High Electron Mobility Transistors (HEMT) fabricated from Gallium Nitride.

    Abstract translation: 为采用N路径共源共栅输出开关的开关输出数模转换器提供技术。 一个示例系统可以包括并联耦合到电流模式数模转换器（DAC）电路的输出级的多个共源共栅晶体管。 该系统还可以包括多个控制端口，每个控制端口耦合到一个共源共栅晶体管的栅极。 该系统还可以包括多个输出端口，每个输出端口耦合到一个共源共栅晶体管。 串联晶体管被配置为响应于施加到晶体管的控制端口的路由控制信号而将DAC的输出级切换到晶体管的输出端口。 共源共栅晶体管是由氮化镓制造的高电子迁移率晶体管（HEMT）。

    N-PATH CASCODE TRANSISTOR OUTPUT SWITCH FOR A DIGITAL TO ANALOG CONVERTER
    7.
    发明申请
    N-PATH CASCODE TRANSISTOR OUTPUT SWITCH FOR A DIGITAL TO ANALOG CONVERTER 有权
    用于数字转换器的N路数字晶体管输出开关

    公开(公告)号：US20160173113A1

    公开(公告)日：2016-06-16

    申请号：US14958051

    申请日：2015-12-03

    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

    Inventor： Joseph D. Cali ,  Lawrence J. Kushner ,  Steven E. Turner

    IPC: H03M1/06 ,  H01L29/20 ,  H01L29/16 ,  H01L27/06 ,  H01L29/772 ,  H01L29/737 ,  H01L29/73 ,  H03M1/66 ,  H01L29/778

    CPC classification number: H03M1/0626 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0617 ,  H01L27/088 ,  H03K17/693 ,  H03M1/66 ,  H03M1/742

    Abstract: Techniques are provided for a switched output digital to analog converter employing an N-path cascode output switch. An example system may include a plurality of cascode transistors coupled in parallel to an output stage of a current mode digital to analog converter (DAC) circuit. The system may also include a plurality of control ports, each of the control ports coupled to a gate of one of the cascode transistors. The system may further include a plurality of output ports, each output port coupled to one of the cascode transistors. The cascode transistors are configured to switch the output stage of the DAC to the output port of the transistor in response to a routing control signal applied to the control port of the transistor. The cascode transistors are High Electron Mobility Transistors (HEMT) fabricated from Gallium Nitride.

    Abstract translation: 为采用N路径共源共栅输出开关的开关输出数模转换器提供技术。 一个示例系统可以包括并联耦合到电流模式数模转换器（DAC）电路的输出级的多个共源共栅晶体管。 该系统还可以包括多个控制端口，每个控制端口耦合到一个共源共栅晶体管的栅极。 该系统还可以包括多个输出端口，每个输出端口耦合到一个共源共栅晶体管。 串联晶体管被配置为响应于施加到晶体管的控制端口的路由控制信号而将DAC的输出级切换到晶体管的输出端口。 共源共栅晶体管是由氮化镓制造的高电子迁移率晶体管（HEMT）。

    High-frequency clock distribution and alignment system
    8.
    发明授权
    High-frequency clock distribution and alignment system 有权

    公开(公告)号：US10698441B2

    公开(公告)日：2020-06-30

    申请号：US15984841

    申请日：2018-05-21

    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

    Inventor： Joseph D. Cali ,  Steven E. Turner

    IPC: G06F1/00 ,  G06F1/12 ,  G06F1/08 ,  G06F1/10

    Abstract: A clock distribution and alignment system includes at least three clock generators, each including a clock receiver circuit to receive a first clock signal having a first frequency, and a clock divider circuit to divide the received first clock signal into a second clock signal having a second frequency lower than the first frequency, each of two or more of the clock generators further including a phase detector circuit to compare the phase of the second clock signal with the phase of the second clock signal for a next one of the clock generators, and a clock adjuster circuit to adjust the phase of the received first clock signal based on the compared phases of the second clock signals. In some cases, the clock adjuster circuit is further to align the phases of the second clock signals to within a predefined tolerance of each other.

    Phase coherent frequency synthesis
    10.
    发明授权
    Phase coherent frequency synthesis 有权

    公开(公告)号：US11652488B2

    公开(公告)日：2023-05-16

    申请号：US17689605

    申请日：2022-03-08

    Applicant: BAE Systems Information and Electronic Systems Integration Inc.

    Inventor： Steven E. Turner ,  Joseph D. Cali

    IPC: H03L7/197 ,  H03L7/093 ,  H03M3/00 ,  G06F1/02

    CPC classification number: H03L7/093 ,  G06F1/022 ,  H03L7/1976 ,  H03M3/30

    Abstract: Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.

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